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參數資料
| 型號： | MM54HC137 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 3-to-8 Line Decoder With Address Latches (Inverted Output) |
| 中文描述： | 3至8線路解碼器，地址鎖存器（倒輸出） |
| 文件頁數： | 3/6頁 |
| 文件大小： | 131K |
| 代理商： | MM54HC137 |
AC Electrical Characteristics
V
CC
e
5V, T
A
e
25
§
C, C
L
e
15 pF, t
r
e
t
f
e
6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
S
t
H
t
W
AC Electrical Characteristics
C
L
e
50 pF, t
r
e
t
f
e
6 ns (unless otherwise specified)
Maximum Propagation Delay, A, B or C to any Y Output
14
29
ns
Maximum Propagation Delay, A, B or C to any Y Output
20
42
ns
Maximum Propagation Delay G2 to any Y Output
12
22
ns
Maximum Propagation Delay G2 to any Y Output
15
34
ns
Maximum Propagation Delay G1 to any Output
13
25
ns
Maximum Propagation Delay GL to any Output
17
34
ns
Maximum Propagation GL to Output
15
30
ns
Maximum Propagation Delay GL to Output
22
34
ns
Minimum Setup Time at A, B and C Inputs
20
ns
Minimum Hold Time at A, B and C Inputs
0
ns
Minimum Pulse Width of Enabling Pulse at GL
16
ns
T
A
e
25
§
C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A
eb
40 to 85
§
C
Guaranteed Limits
T
A
eb
55 to 125
§
C
Units
Typ
t
PLH
Maximum Propagation Delay
A, B or C to any Y Output
2.0V
4.5V
6.0V
85
17
14
170
34
29
214
43
36
253
51
43
ns
ns
ns
t
PHL
Maximum Propagation Delay
A, B or C to any Y Output
2.0V
4.5V
6.0V
120
24
20
240
48
41
302
60
51
358
72
61
ns
ns
ns
t
PLH
Maximum Propagation Delay
G2 to any Y Output
2.0V
4.5V
6.0V
65
13
11
130
26
22
164
33
28
194
39
33
ns
ns
ns
t
PLH
Maximum Propagation
Delay G1 to Output
2.0V
4.5V
6.0V
75
15
13
150
30
26
189
38
32
224
45
38
ns
ns
ns
t
PHL
Maximum Propagation
Delay G1 to Output
2.0V
4.5V
6.0V
98
20
17
195
39
33
246
49
42
291
58
49
ns
ns
ns
t
PLH
Maximum Propagation
Delay GL to Output
2.0V
4.5V
6.0V
88
18
15
175
35
30
221
44
37
261
52
44
ns
ns
ns
t
PHL
Maximum Propagation
Delay GL to Output
2.0V
4.5V
6.0V
125
25
21
250
50
43
315
63
54
373
75
63
ns
ns
ns
t
PHL
Maximum Propagation Delay
G2, to any Y Output
2.0V
4.5V
6.0V
98
20
17
195
39
33
246
49
42
291
58
49
ns
ns
ns
t
S
Minimum Setup Time
at A, B and C inputs
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
t
H
Minimum Hold Time
at A, B and C inputs
2.0V
4.5V
6.0V
50
10
8
63
13
11
75
15
13
ns
ns
ns
t
TLH
, t
THL
Output Rise and
Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
t
W
Minimum Pulse Width
of Enabling Pulse at GL
2.0V
4.5V
6.0V
80
16
14
100
20
18
120
24
21
ns
ns
ns
C
PD
Power Dissipation
Capacitance (Note 5)
75
pF
C
IN
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption, I
S
e
C
PD
V
CC
f
a
I
CC
.
Maximum Input Capacitance
5
10
10
10
pF
3
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相關代理商/技術參數 |
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|---|---|
| MM54HC137J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:3-to-8 Line Decoder With Address Latches (Inverted Output) |
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