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參數資料
| 型號： | MM54HC85 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 4-Bit Magnitude Comparator |
| 中文描述： | 4位數值比較 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 168K |
| 代理商： | MM54HC85 |
TL/F/5205
M
November 1995
MM54HC85/MM74HC85
4-Bit Magnitude Comparator
General Description
The MM54HC85/MM74HC85 is a 4-bit magnitude compara-
tor that utilizes advanced silicon-gate CMOS technology. It
is designed for high speed comparison of two four bit words.
This circuit has eight comparison inputs, 4 for each word;
three cascade inputs (A
k
B, A
l
B, A
e
B); and three deci-
sion outputs (A
k
B, A
l
B, A
e
B). The result of a comparison
is indicated by a high level on one of the decision outputs.
Thus it may be determined whether one word is ‘‘greater
than,’’ ‘‘less than,’’ or ‘‘equal to’’ the other word. By con-
necting the outputs of the least significant stage to the cas-
cade inputs of the next stage, words of greater than four bits
can be compared. In addition the least significant stage
must have a high level applied to the A
e
B input, and a low
level to the A
k
B, and A
l
B inputs.
The comparator’s outputs can drive 10 low power Schottky
TTL (LS-TTL) equivalent loads, and is functionally, and pin
equivalent to the 54LS85/74LS85. All inputs are protected
from damage due to static discharge by diodes to V
CC
and
ground.
Features
Y
Typical propagation delay: 27 ns
Y
Wide operating voltage range: 2–6V
Y
Low input current: 1
m
A maximum
Y
Low quiescent current: 80
m
A maximum (74HC Series)
Y
Output drive capability: 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TL/F/5205–1
Order Number MM54HC85 or MM74HC85
Truth Table
Comparing
Inputs
Cascading
Inputs
Outputs
A3, B3
A2, B2
A1, B1
A0, B0
A
l
B
A
k
B
A
e
B
A
l
B
A
k
B
A
e
B
A3
l
B3
A3
k
B3
A3
e
B3
A3
e
B3
A3
e
B3
A3
e
B3
A3
e
B3
A3
e
B3
A3
e
B3
A3
e
B3
A3
e
B3
A3
e
B3
A3
e
B3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
H
L
X
X
X
X
X
X
X
X
L
H
X
H
L
X
X
X
X
X
X
X
X
L
L
H
L
L
H
L
H
L
H
L
H
L
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
A2
l
B2
A2
k
B2
A2
e
B2
A2
e
B2
A2
e
B2
A2
e
B2
A2
e
B2
A2
e
B2
A2
e
B2
A2
e
B2
A2
e
B2
A1
l
B1
A1
k
B1
A1
e
B1
A1
e
B1
A1
e
B1
A1
e
B1
A1
e
B1
A1
e
B1
A1
e
B1
A0
l
B0
A0
k
B0
A0
e
B0
A0
e
B0
A0
e
B0
A0
e
B0
A0
e
B0
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
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|---|---|
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