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參數資料
| 型號： | MM54HC85 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 4-Bit Magnitude Comparator |
| 中文描述： | 4位數值比較 |
| 文件頁數： | 3/6頁 |
| 文件大?。?/td> | 168K |
| 代理商： | MM54HC85 |
AC Electrical Characteristics
V
CC
e
5V, T
A
e
25
§
C, C
L
e
15 pF, t
r
e
t
f
e
6 ns
Symbol
Parameter
t
PHL
, t
PLH
Maximum Propagation Delay Data Input to A
k
B or A
l
B
t
PHL
, t
PLH
Maximum Propagation Delay A
e
B Input to A
e
B Output
t
PHL
, t
PLH
Maximum Propagation Delay Cascade Input to Output
t
PHL
, t
PLH
Maximum Propagation Delay Data Input to A
e
B
Conditions
Typ
20
12
13
20
Limit
36
20
26
30
Units
ns
ns
ns
ns
AC Electrical Characteristics
C
L
e
50 pF, t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25
§
C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A
eb
40 to 85
§
C
Guaranteed Limits
265
53
45
221
44
37
158
32
27
195
39
33
95
19
16
10
T
A
eb
55 to 125
§
C
Units
Typ
100
21
18
88
18
15
63
13
11
70
16
13
25
7
6
5
80
t
PHL
, t
PLH
Maximum Propagation
Delay Data Input to
Output
Maximum Propagation Delay
Data Input to A
e
B Output
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
210
42
36
175
35
30
125
25
21
155
31
26
75
15
13
10
313
63
53
261
52
44
186
37
32
231
46
39
110
22
19
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
t
PHL
, t
PLH
t
PHL
, t
PLH
Maximum Propagation Delay
A
e
B Input to A
e
B Output
t
PHL
, t
PLH
Maximum Propagation
Delay Cascade Input
to Output (except A
e
B)
Maximum Output Rise
and Fall Time
t
TLH
, t
THL
C
IN
C
PD
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
e
C
PD
V
CC
f
a
I
CC
.
Maximum Input Capacitance
Power Dissipation Capacitance
(Note 5)
Typical Application
TL/F/5205–4
Cascading Comparators
3
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相關代理商/技術參數 |
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|---|---|
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