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參數資料
| 型號： | MM54HCT573WM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop |
| 中文描述： | HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 127K |
| 代理商： | MM54HCT573WM |
TL/F/10627
M
M
PRELIMINARY
February 1990
MM54HCT573/MM74HCT573
TRI-STATE
é
Octal D-Type Latch
MM54HCT574/MM74HCT574
TRI-STATE Octal D-Type Flip-Flop
General Description
The MM54HCT573/MM74HCT573 octal D-type latches and
MM54HCT574/MM74HCT574 Octal D-type flip flops ad-
vanced silicon-gate CMOS technology, which provides the
inherent benefits of low power consumption and wide power
supply range, but are LS-TTL input and output characteristic
& pin-out compatible. The TRI-STATE outputs are capable
of driving 15 LS-TTL loads. All inputs are protected from
damage due to static discharge by internal diodes to V
CC
and ground.
When the MM54HCT573/MM74HCT573 LATCH ENABLE
input is high, the Q outputs will follow the D inputs. When
the LATCH ENABLE goes low, data at the D inputs will be
retained at the outputs until LATCH ENABLE returns high
again. When a high logic level is applied to the OUTPUT
CONTROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The MM54HCT574/MM74HCT574 are positive edge trig-
gered flip-flops. Data at the D inputs, meeting the setup and
hold time requirements, are transferred to the Q outputs on
positive going transitions of the CLOCK (CK) input. When a
high logic level is applied to the OUTPUT CONTROL (OC)
input, all outputs go to a high impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
MM54HCT/MM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
devices. These parts are also plug in replacements for LS-
TTL devices and can be used to reduce power consumption
in existing designs.
Features
Y
TTL input characteristic compatible
Y
Typical propagation delay: 18 ns
Y
Low input current: 1
m
A maximum
Y
Low quiescent current: 80
m
A maximum
Y
Compatible with bus-oriented systems
Y
Output drive capability: 15 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TL/F/10627–1
Top View
Order Number MM54HCT573
*
or MM74HCT573
*
TL/F/10627–2
Top View
Order Number MM54HCT574
*
or MM74HCT574
*
*
Please look into Section 8, Appendix D for availability of various package types.
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
相關PDF資料 |
PDF描述 |
|---|---|
| MM54HCT574 | TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop |
| MM54HCT574N | TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop |
| MM54HCT574WM | TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop |
| MM54HCT643 | Inverting Octal TRI-STATE Transceiver |
| MM54HCT640 | Inverting Octal TRI-STATE Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MM54HCT574 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop |
| MM54HCT574N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop |
| MM54HCT574WM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop |
| MM54HCT640 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Inverting Octal TRI-STATE Transceiver |
| MM54HCT640J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Inverting Octal TRI-STATE Transceiver |
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