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參數資料
| 型號： | MM74HC76N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 1.5A 280kHz/560kHz Boost Regulators; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數： | 3/6頁 |
| 文件大?。?/td> | 136K |
| 代理商： | MM74HC76N |
AC Electrical Characteristics
V
CC
e
5V, T
A
e
25
§
C, C
L
e
15 pF, t
r
e
t
f
e
6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed Limit
Units
f
MAX
Maximum Operating Frequency
50
30
MHz
t
PHL
, t
PLH
Maximum Propagation Delay Clock to Q or Q
16
21
ns
t
PHL
, t
PLH
Maximum Propagation Delay Clear to Q or Q
21
26
ns
t
PHL
, t
PLH
Maximum Propagation Delay Preset to Q or Q
23
28
ns
t
REM
Minimum Removal Time
10
20
ns
t
s
Minimum Setup Time J or K to Clock
14
20
ns
t
H
Minimum Hold Time J or K to Clock
b
3
0
ns
t
W
Minimum Pulse Width Preset, Clear or Clock
10
16
ns
AC Electrical Characteristics
C
L
e
50 pF, t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25
§
C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A
eb
40 to 85
§
C
T
A
eb
55 to 125
§
C
Units
Typ
Guaranteed Limits
f
MAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
9
5
4
3
MHz
MHz
MHz
45
53
27
31
21
24
18
20
t
PHL
, t
PLH
Maximum Propagation
Delay Clock to Q or Q
2.0V
4.5V
6.0V
100
20
17
126
25
21
160
31
27
183
37
32
ns
ns
ns
t
PHL
, t
PLH
Maximum Propagation
Delay Clear to Q or Q
2.0V
4.5V
6.0V
126
25
21
155
31
26
191
39
33
250
47
40
ns
ns
ns
t
PHL
, t
PLH
Maximum Propagation
Delay, Preset to Q or Q
2.0V
4.5V
6.0V
137
27
23
165
33
28
210
41
35
240
50
40
ns
ns
ns
t
REM
Minimum Removal Time
Preset or Clear
to Clock
2.0V
4.5V
6.0V
55
11
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
t
s
Minimum Setup Time
J or K to Clock
2.0V
4.5V
6.0V
77
15
13
100
20
17
125
25
21
150
30
25
ns
ns
ns
t
H
Minimum Hold Time
J or K from Clock
2.0V
4.5V
6.0V
b
3
b
3
b
3
0
0
0
0
0
0
0
0
0
ns
ns
ns
t
W
Minimum, Pulse Width,
Preset, Clear or Clock
2.0V
4.5V
6.0V
55
11
9
80
16
14
100
20
18
120
24
21
ns
ns
ns
t
TLH
, t
THL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
t
r
, t
f
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
C
PD
Power Dissipation
Capacitance (Note 5)
(per flip-flop)
80
pF
C
IN
Maximum Input
Capacitance
5
10
10
10
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption, I
S
e
C
PD
V
CC
f
a
I
CC
.
3
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