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參數資料
| 型號： | MMKR-29C516E-31SB |
| 廠商： | ATMEL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 16 Bit Flow Through EDAC Error Detection And Correction unit |
| 中文描述： | CMOS SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, TRUE OUTPUT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數： | 4/16頁 |
| 文件大小： | 94K |
| 代理商： | MMKR-29C516E-31SB |
29C516E
4
Rev. D (09 Dec. 97)
3.4. Pin Description
Table 1:
Name
Pin Description
I/O
Active
Description
Buses
U1D
[
0..15
]
53,49..47,45..42,40..37,35..33,28
I/O*
High
User 1 Data Bus
U2D
[
0..15
]
23..20,18..15,13..10,8..5
I/O*
High
User 2 Data Bus
Μ
D
[
0..15
]
59..62,64..67,69..72,74..77
I/O*
High
Memory Data Bus
Μ
C
[
0..7
]
83..86,88..91
I/O*
High
Memory Check–bit Bus
Error Flags
CERR
26
O
Low
Correctable Error
NCERR
25
O
Low
Uncorrectable Error
General Control Signals
CORRECT
98
I*
High
When active, the EDAC is in CORRECT mode. If low,
the EDAC is in DETECT mode.
SYNCHK
97
I*
Low
Selects the Syndrome bits (high byte) and the Check–bits
(low byte) to be driven on the selected User Data Bus.
N22
27
I*
High
When active, the EDAC uses 6 check–bits. If low, the
EDAC uses 8 check–bits in memory read.
TRANS
96
I*
H/L
Selects the Data path to be used. If high, the EDAC
access the memory, if low, the EDAC access the transfer
buffer.
U2/U1
95
I*
H/L
Selects who is the master of User 1 and User 2. The
master is responsible for applying RD/WRx, MEMx, and
ENx signals in a correct way.
User 1 Control Signals
RD/WRT
55
I*
H/L
User 1 Read/Write signal
EN1
56
I*
Low
User 1 Output Enable
MEM1
57
I*
Low
User 1 Memory Select
User 1 Control Signals
RD/WR2
99
I*
H/L
User 2 Read/Write signal
EN2
94
I*
Low
User 2 Output Enable
MEM2
3
I*
Low
User 2 Memory Select
Power (Buffers)
VCC
B
9,19,32,41,54,63,73,87
I
–
Buffers supply (5 V nominal)
GND
B
4,14,24,36,46,58,68,78,92
I
–
Buffers 0 V nominal reference
Power (Core)
VCC
C
100
I
–
Core supply (5 V nominal)
GND
C
93
I
–
Core 0 V reference
* Pull–up buffers
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