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參數資料
| 型號： | MPC9351FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9351 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 356K |
| 代理商： | MPC9351FAR2 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9351/D
Rev 2, 05/2003
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
107
Low Voltage PLL Clock Driver
The MPC9351 is a 2.5V and 3.3V compatible, PLL based clock gener-
ator targeted for high performance clock distribution systems. With output
frequencies of up to 200 MHz and a maximum output skew of 150 ps the
MPC9351 is an ideal solution for the most demanding clock tree designs.
The device offers 9 low skew clock outputs, each is configurable to sup-
port the clocking needs of the various high-performance microprocessors
including the PowerQuicc II integrated communication microprocessor.
The extended temperature range of the MPC9351 supports telecommu-
nication and networking requirements.The devices employs a fully differ-
ential PLL design to minimize cycle-to-cycle and long-term jitter.
Features
9 outputs LVCMOS PLL clock generator
25 - 200 MHz output frequency range
Fully integrated PLL
2.5V and 3.3V compatible
Compatible to various microprocessors such as PowerQuicc II
Supports networking, telecommunications and computer applications
Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
LVPECL and LVCMOS compatible inputs
External feedback enables zero-delay configurations
Output enable/disable and static test mode (PLL enable/disable)
Low skew characteristics: maximum 150 ps output-to-output
Cycle-to-cycle jitter max. 22 ps RMS
32 lead LQFP package
Ambient Temperature Range –40°C to +85°C
Functional Description
The MPC9351 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal opera-
tion of the MPC9351 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback path. The
reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected to
match the VCO frequency range. With available output dividers of divide-by-2, divide-by-4 and divide-by-8 the internal VCO of
the MPC9351 is running at either 2x, 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs
is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using
the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2
and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input
(TCLK). The MPC9351 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test
mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended for
system diagnostics, test and debug purpose. This test mode is fully static and the minimum clock frequency specification does
not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL
to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked
loop, also enabling the PLL to recover to normal operation. The MPC9351 is fully 2.5V and 3.3V compatible and requires no
external loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS
compatible levels with the capability to drive terminated 50
W transmission lines. For series terminated transmission lines, each
of the MPC9351 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a
7x7 mm2 32-lead LQFP package.
Application Information
The fully integrated PLL of the MPC9351 allows the low skew outputs to lock onto a clock input and distribute it with essentially
zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between
the outputs and the reference signal.
2
FA SUFFIX
LQFP PACKAGE
CASE 873A
MPC9351
LOW VOLTAGE
2.5V AND 3.3V PLL
CLOCK GENERATOR
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MPC9352 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR |
| MPC9352AC | 功能描述:鎖相環 - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9352ACR2 | 功能描述:時鐘發生器及支持產品 FSL 1-11 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9352FA | 功能描述:鎖相環 - PLL 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9352FAR2 | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
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