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參數資料
| 型號： | MPC93H51FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32 |
| 文件頁數： | 1/15頁 |
| 文件大?。?/td> | 368K |
| 代理商： | MPC93H51FA |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order number: MPC93H51/D
Rev 2, 2/2004
Motorola, Inc. 2004
Low Voltage PLL Clock Driver
The MPC93H51 is a 3.3V compatible, PLL based clock generator
targeted for high performance clock distribution systems. With output
frequencies of up to 240 MHz and a maximum output skew of 150 ps
the MPC93H51 is an ideal solution for the most demanding clock tree
designs. The device offers 9 low skew clock outputs, each is config-
urable to support the clocking needs of the various high-performance
microprocessors including the PowerQuicc II integrated communica-
tion microprocessor. The devices employs a fully differential PLL de-
sign to minimize cycle-to-cycle and long-term jitter.
Features
9 outputs LVCMOS PLL clock generator
25 - 240 MHz output frequency range
Fully integrated PLL
Compatible to various microprocessors such as PowerQuicc II
Supports networking, telecommunications and computer
applications
Configurable outputs: divide-by-2, 4 and 8 of VCO frequency
LVPECL and LVCMOS compatible inputs
External feedback enables zero-delay configurations
Output enable/disable and static test mode (PLL enable/disable)
Low skew characteristics: maximum 150 ps output-to-output
32 lead LQFP package
Ambient Temperature Range 0°C to +70°C
Pin & Function Compatible with the MPC951
Functional Description
The MPC93H51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal
operation of the MPC93H51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL
feedback path. The reference clock frequency and the output divider for the feedback path determine the VCO
frequency. Both must be selected to match the VCO frequency range. With available output dividers of divide-by-4 and
divide-by-8 the internal VCO of the MPC93H51 is running at either 4x or 8x of the reference clock frequency. The
frequency of the QA, QB, QC and QD outputs is either the one half, one fourth or one eighth of the selected VCO
frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively.
The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The REF_SEL pin selects the differential
LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input (TCLK). The MPC93H51 also provides a static
test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock
is routed directly to the output dividers bypassing the PLL. The test mode is intended for system diagnostics, test and
debug purpose. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs
can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes the PLL to loose lock
due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase locked loop,
also enabling the PLL to recover to normal operation. The MPC93H51 is 3.3V compatible and requires no external loop
filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS
compatible levels with the capability to drive terminated 50
transmission lines. For series terminated transmission
lines, each of the MPC93H51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The
device is packaged in a 7x7 mm2 32-lead LQFP package.
Application Information
The fully integrated PLL of the MPC93H51 allows the low skew outputs to lock onto a clock input and distribute it with
essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes
phase offset between the outputs and the reference signal.
MPC93H51
FA SUFFIX
LQFP PACKAGE
CASE 873A-03
LOW VOLTAGE 3.3 V
PLL CLOCK GENERATOR
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MPC93H52AC | 功能描述:時鐘發生器及支持產品 FSL 1-11 LVCMOS PLL Clock Generator, hig RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93H52ACR2 | 功能描述:IC CLK GEN ZD 1:11 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC93H52FA | 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93R51 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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