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參數資料
| 型號： | MPC951FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 951 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁數： | 1/8頁 |
| 文件大?。?/td> | 303K |
| 代理商： | MPC951FAR2 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC951/D
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
160
Low Voltage PLL Clock Driver
The MPC951 is a 3.3V compatible, PLL based clock driver device tar-
geted for high performance clock tree designs. With output frequencies of
up to 180MHz and output skews of 375ps the MPC951 is ideal for the
most demanding clock tree designs. The devices employ a fully differen-
tial PLL design to minimize cycle–to–cycle and long term jitter. This pa-
rameter is of significant importance when the clock driver is providing the
reference clock for PLL’s on board today’s microprocessors and ASiC’s.
The devices offer 9 low skew outputs, the outputs are configurable to
support the clocking needs of the various high performance microproces-
sors.
Fully Integrated PLL
Output Frequency up to 180MHz
Outputs Disable in High Impedance
Compatible with PowerPC, Intel and High Performance RISC Mi-
croprocessors
LQFP Packaging
Output Frequency Configurable
±100ps Typical Cycle–to–Cycle Jitter
The MPC951 uses a differential PECL reference input and an external
feedback input. These features allow for the MPC951 to be used as a
zero delay, low skew fanout buffer. In addition, the external feedback al-
lows for a wider variety of input–to–output frequency relationships. The
REF_SEL pin allows for the selection of an alternate LVCMOS input clock
to be used as a test clock or to provide the reference for the PLL from an
LVCMOS source.
The MPC951 is fully 3.3V compatible and require no external loop filter components. All inputs accept LVCMOS or LVTTL
compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50
transmission lines. Select
inputs do not have internal pull–up/pull–down resistors and thus must be set externally. If the PECL_CLK inputs are not used,
they can be left open. For series terminated 50
lines, each of the MPC951 outputs can drive two traces giving the device an
effective fanout of 1:18. The device is packaged in a 7x7mm 32–lead LQFP package to provide the optimum combination of
board density and performance.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
Rev 0
2
MPC951
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A–02
See Upgrade Product – MPC9351
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MPC952 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC953 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC958 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9600 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER |
| MPC9600AE | 功能描述:時鐘發生器及支持產品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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