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參數資料
| 型號： | MPC962304D-1R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 962304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOIC-8 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 84K |
| 代理商： | MPC962304D-1R2 |
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
501
Freescale Semiconductor, Inc.
TECHNICAL DATA
Order number: MPC962304
Rev 0, 07/2004
3.3 V Zero Delay Buffer
The MPC962304 is a 3.3 V Zero Delay Buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom and other high-
performance applications. The MPC962304 uses an internal PLL and an
external feedback path to lock its low-skew clock output phase to the reference
clock phase, providing virtually zero propagation delay. The input-to-output
skew is guaranteed to be less than 250 ps and output-to-output skew is
guaranteed to be less than 200 ps.
Features
1:4 outputs LVCMOS zero-delay buffer
Zero input-output propagation delay, adjustable by the capacitive load on
FBK input
Multiple Configurations, See Table 1. Available MPC962304
Multiple low-skew outputs
–
200 ps max output-output skew
–
500 ps max device-device skew
Supports a clock I/O frequency range of 10 MHz to 133 MHz
Low jitter, 200 ps max cycle-cycle
8-pin SOIC package
Single 3.3 V supply
Ambient temperature range: –40
°C to +85°C
Compatible with the CY2304
Functional Description
The MPC962304 has two banks of two outputs each. The MPC962304 PLL enters a power down state when there are no rising
edges on the REF input. During this state, all of the outputs are in tristate. When the PLL is turned off, there is less than 25
A of
current draw.
Multiple MPC962304 devices can accept and distribute the same input clock throughout the system. In this situation, the difference
between the output skews of two devices will be less than 500 ps.
The MPC962304 is offered in two configurations. In the -1 version, the reference frequency is reproduced by the PLL and provided
to the outputs.
The MPC962304-2 provides 1/2X and 2X the reference frequency at the output banks.
MPC962304
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-06
8-pin SOIC
Top View
Pin Configuration
CLKA1
CLKA2
FBK
PLL
/2
REF
Extra Divider (–2)
Block Diagram
1
2
3
4
8
7
6
5
FBK
VDD
CLKB2
CLKB1
REF
CLKA1
CLKA2
GND
CLKB1
CLKA2
CLKB2
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MPC962305 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
| MPC962305D-1 | 功能描述:IC CLOCK BUFFER 1:5 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MPC962305D-1H | 功能描述:IC CLOCK BUFFER 1:5 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MPC962305D-1HR2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
| MPC962305D-1R2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
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