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參數(shù)資料
| 型號(hào)： | MPC980 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual 3.3V PLL Clock Generator(雙3.3V PLL時(shí)鐘發(fā)生器) |
| 中文描述： | 雙3.3V的PLL時(shí)鐘發(fā)生器（雙3.3鎖相環(huán)時(shí)鐘發(fā)生器） |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 133K |
| 代理商： | MPC980 |
SEMICONDUCTOR TECHNICAL DATA
1
REV 2
Motorola, Inc. 1998
1/98
The MPC980 is a 3.3V dual PLL clock generator targeted for high end
Pentium
and PowerPC
603/604 personal computers. The MPC980
synthesizes processor as well as PCI clocks from a 14.31818MHz
external crystal. In addition the device provides two buffered outputs of
the 14.31818MHz crystal as well as a 40MHz SCSI clock, a 24MHz floppy
clock and a 12MHz keyboard clock. One of the buffered 14.31818MHz
outputs can be configured to provide a 16MHz output rather than the
second copy of the 14.31818MHz output.
Provides Processor and System Clocks for Pentium
Designs
Provides Processor and System Clocks for PowerPC
603/604
Designs
Two Fully Integrated Phase–Locked Loops
Cycle–to–Cycle Jitter of
±
150ps
Operates from 3.3V Supply
52–Lead LQFP Packaging
The processor clock outputs of the MPC980 can be programmed to
provide 50, 60 or 66MHz. Under all processor output frequencies the PCI
clock outputs will be equal to one half the processor clock outputs. The
PCI outputs will run synchronously to the processor clock outputs. There
are a total of ten output clocks which can be split into a group of four and a
group of six. Either group can be configured as processor or PCI clocks.
Each of the outputs can drive two series terminated transmission lines
allowing for the driving of up to twelve independent processor loads and
eight PCI clock loads. A pin selectable option is available to delay the PCI
clock outputs relative to the processor clocks. The amount of delay is a
function of the processor clock frequency and varies from 2ns to 6ns.
The output jitter of the the PLL at 66MHz output is
±
150ps peak–to–peak, cycle–to–cycle (the worst case deviation of the clock
period is guaranteed to be less than
±
150ps). The skews between one processor clock and any other processor clock (or one
PCI clock to any other PCI clock) is 350ps. The worst case skew between the processor clocks and the PCI clocks is 500ps.
An output enable pin is provided to tristate all of the outputs for board level test. In addition a testing mode is provided to allow
for the bypass of the PLL’s for board level functional debug.
Pentium is a trademark of Intel Corporation. PowerPC is a trademark of International Business
Machines Corporation.
DUAL 3.3V PLL
CLOCK GENERATOR
FA SUFFIX
52–LEAD LQFP PACKAGE
CASE 848D–03
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