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參數(shù)資料
| 型號： | MPC9990FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 203K |
| 代理商： | MPC9990FAR2 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9990/D
Rev 5, 03/2002
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
287
Product Preview
Low Voltage PLL Clock
Driver
The MPC9990 is a low voltage PLL clock driver designed for high speed
clock generation and distribution in high performance computer, workstation
and server applications. The clock driver accepts a LVPECL compatible
clock signal and provides 10 low skew, differential HSTL1 compatible out-
puts, one HSTL compatible output for system synchronization purposes and
one HSTL compatible PLL feedback output. The device operates from a
dual voltage supply: 3.3 V for the core logic and 1.8 V for the HSTL outputs.
The fully integrated PLL supports an input frequency range of 75 to 287.5
MHz. The output frequencies are configurable.
Supports high performance HSTL clock distribution systems
Compatible to IA64 processor systems
Fully Integrated PLL, differential design
Core logic operates from 3.3 V power supply
HSTL outputs operate from a 1.8 V supply
Programmable frequency by output bank
10 HSTL compatible outputs (two banks)
HSTL compatible PLL feedback output
HSTL compatible sychronization output (QSYNC)
Max. skew of 80 ps within output bank
Zero–delay capability: max. SPO (tpd) window of 150 ps
LVPECL compatible clock input, LVCMOS compatible control inputs
Temperature range of 0 to +70°C
The MPC9990 provides output clock frequencies required for high–performance computer system optimization. The device
drives up to 10 differential clock loads within the frequency range of 75 to 287.5 MHz. The 10 outputs are organized in 2 banks of
3 and 7 differential outputs. In the standard configuration the QFB output pair is connected to the FB input pair closing the PLL
loop and enabling zero delay operation from the CLK input to the outputs. Bank B outputs are frequency and phase aligned to the
CLK input, providing exact copies of the high–speed input signal. Bank A outputs are configured to operate at slower speeds
driving the system bus devices. The output frequency ratio of bank A to bank B is adjustable (for available ratios, see “MPC9990
Application: CPU to System Bus Frequency Ratios” on page 288) for system optimization. In a computer application, bank B
outputs generate the clock signals for the devices operating at the CPU frequency, while Bank A outputs are configured to drive
the clock signals for the devices running at lower speeds (system clock). Four individual frequency ratios are available, providing
a high degree of flexibility. The frequency ratios between CPU clock and system clock provided by the MPC9990 are listed in the
table “Output configuration” on page 290.
The QSYNC output functionality is designed for system synchronization purpose. QSYNC is asserted at coincident rising
edges of CPU (bank B and QFB signal) and slower system clock (bank A) outputs (see “QSYNC Phase Relation Diagram” on
page 290), providing baseline timing in systems with fractional clocks. The QSYNC output is asserted for one QFB high pulse,
centered on the rising QFB output.
Figure 1. MPC9990 Application Example
MPC9990
250 MHz
QFB
FB
QSYNC
QB[0:2]
CLK
QA[0:6]
250 MHz
CPU clocks
System clocks: 250, 200,
187, 125 MHz
System synchronization
1. In order to minimize output–to–output skew, HSTL outputs of the MPC9990 are generated with an open emitter architecture. For output termina-
tion, see ”HSTL Output Termination and AC Test Reference” on page 291.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
2
MPC9990
LOW VOLTAGE
DIFFERENTIAL PECL–HSTL
PLL CLOCK DRIVER
FA SUFFIX
48–LEAD LQFP PACKAGE
CASE 932
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