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參數資料
| 型號： | MPSA70RLRE |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 小信號晶體管 |
| 英文描述： | 100 mA, 40 V, PNP, Si, SMALL SIGNAL TRANSISTOR, TO-92 |
| 封裝： | PLASTIC, TO-226AA, 3 PIN |
| 文件頁數： | 34/37頁 |
| 文件大小： | 490K |
| 代理商： | MPSA70RLRE |
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MPSA70
2–663
Motorola Small–Signal Transistors, FETs and Diodes Device Data
Figure 17. Thermal Response
t, TIME (ms)
1.0
0.01
r(t)
TRANSIENT
THERMAL
RESIST
ANCE
(NORMALIZED)
0.01
0.02
0.03
0.05
0.07
0.1
0.2
0.3
0.5
0.7
0.02
0.05
0.1
0.2
0.5
1.0
2.0
5.0
10
20
50
100
200
500
1.0 k 2.0 k
5.0 k 10 k
20 k
50 k 100 k
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
DUTY CYCLE, D = t1/t2
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1 (SEE AN–569)
Z
θJA(t) = r(t) RθJA
TJ(pk) – TA = P(pk) Z
θJA(t)
t1
t2
P(pk)
FIGURE 19
Figure 18. Active–Region Safe Operating Area
TJ, JUNCTION TEMPERATURE (°C)
104
–4
0
I C
,COLLECT
OR
CURRENT
(nA)
Figure 19. Typical Collector Leakage Current
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
400
2.0
I C
,COLLECT
OR
CURRENT
(mA)
DESIGN NOTE: USE OF THERMAL RESPONSE DATA
A train of periodical power pulses can be represented by the model
as shown in Figure 19. Using the model and the device thermal
response the normalized effective transient thermal resistance of
Figure 17 was calculated for various duty cycles.
To find Z
θJA(t), multiply the value obtained from Figure 17 by the
steady state value R
θJA.
Example:
Dissipating 2.0 watts peak under the following conditions:
t1 = 1.0 ms, t2 = 5.0 ms (D = 0.2)
Using Figure 17 at a pulse width of 1.0 ms and D = 0.2, the reading of
r(t) is 0.22.
The peak rise in junction temperature is therefore
T = r(t) x P(pk) x RθJA = 0.22 x 2.0 x 200 = 88°C.
For more information, see AN–569.
The safe operating area curves indicate IC–VCE limits of the
transistor that must be observed for reliable operation. Collector load
lines for specific circuits must fall below the limits indicated by the
applicable curve.
The data of Figure 18 is based upon TJ(pk) = 150°C; TC or TA is
variable depending upon conditions. Pulse curves are valid for duty
cycles to 10% provided TJ(pk) ≤ 150°C. TJ(pk) may be calculated from
the data in Figure 17. At high case or ambient temperatures, thermal
limitations will reduce the power than can be handled to values less
than the limitations imposed by second breakdown.
10–2
10–1
100
101
102
103
–2
0
+ 20
+ 40
+ 60
+ 80 + 100 + 120 + 140 + 160
VCC = 30 V
ICEO
ICBO
AND
ICEX @ VBE(off) = 3.0 V
TA = 25°C
CURRENT LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
1.0 ms
10
s
TC = 25°C
1.0 s
dc
4.0
6.0
10
20
40
60
100
200
4.0
6.0
8.0 10
20
40
TJ = 150°C
100
s
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相關代理商/技術參數 |
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| MPSA70RLRM | 功能描述:兩極晶體管 - BJT 100mA 40V PNP RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發射極最大電壓 VCEO:- 40 V 發射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2 |
| MPSA70RLRMG | 功能描述:兩極晶體管 - BJT 100mA 40V PNP RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發射極最大電壓 VCEO:- 40 V 發射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2 |
| MPSA75 | 制造商:CENTRAL 制造商全稱:Central Semiconductor Corp 功能描述:Small Signal Transistors |
| MPSA75_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Darlington Transistors PNP Silicon |
| MPSA75RLRA | 功能描述:達林頓晶體管 500mA 40V PNP RoHS:否 制造商:Texas Instruments 配置:Octal 晶體管極性:NPN 集電極—發射極最大電壓 VCEO:50 V 發射極 - 基極電壓 VEBO: 集電極—基極電壓 VCBO: 最大直流電集電極電流:0.5 A 最大集電極截止電流: 功率耗散: 最大工作溫度:+ 150 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-18 封裝:Reel |
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