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參數資料
| 型號： | MR18R1628AF0-CM8 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | (16Mx16)x2(4/8/16)pcs RIMM Module based on 256Mb A-die, 32s banks,16K/32ms Ref, 2.5V |
| 中文描述： | （16Mx16顯示）× 2（4/8/16）件RIMM的模塊，基于256Mb阿芯片，32秒銀行，16K/32ms參考，為2.5V |
| 文件頁數： | 5/16頁 |
| 文件大小： | 419K |
| 代理商： | MR18R1628AF0-CM8 |
Page 4
Version 1.4 July 2002
MR16R1622(4/8/G)AF0
MR18R1622(4/8/G)AF0(1)
RCOL4..
RCOL0
A73, B73, A71, B71, A69
I
RSL
Column bus. 5-bit bus containing control and address infor-
mation for column accesses.
RCTM
A79
I
RSL
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Positive polarity.
RCTMN
A81
I
RSL
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Negative polarity.
RDQA8..
RDQA0
A91, B91, A89, B89, A87, B87, A85,
B85, A83
I/O
RSL
Data bus A. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM device. RDQA8 is
non-functional on modules x16 RDRAM devices.
RDQB8..
RDQB0
B61, A61, B63, A63, B65, A65, B67,
A67, B69
I/O
RSL
Data bus B. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM device. RDQB8 is
non-functional on modules x16 RDRAM devices.
RROW2..
RROW0
B77, A75, B75
I
RSL
Row bus. 3-bit bus containing control and address information
for row accesses.
RSCK
A59
I
V
CMOS
Serial Clock input. Clock source used to read from and write
to the RDRAM control registers.
SA0
B53
I
SV
DD
Serial Presence Detect Address 0.
SA1
B55
I
SV
DD
Serial Presence Detect Address 1.
SA2
B57
I
SV
DD
Serial Presence Detect Address 2.
SCL
A53
I
SV
DD
Serial Presence Detect Clock.
SDA
A55
I/O
SV
DD
Serial Presence Detect Data (Open Collector I/O).
SIN
B36
I/O
V
CMOS
Serial I/O for reading from and writing to the control registers.
Attaches to SIO0 of the first RDRAM device on the module.
SOUT
A36
I/O
V
CMOS
Serial I/O for reading from and writing to the control registers.
Attaches to SIO1 of the last RDRAM device on the module.
SV
DD
A56, B56
SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1
and SA2.
SWP
A57
I
SV
DD
Serial Presence Detect Write Protect (active high). When low,
the SPD can be written as well as read.
V
CMOS
A35, B35, A37, B37
CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.
Vdd
A41, A42, A54, A58, B41, B42, B54,
B58
Supply voltage for the RDRAM core and interface logic.
Vref
A51, B51
Logic threshold reference voltage for RSL signals.
Signal
Pins
I/O
Type
Description
相關PDF資料 |
PDF描述 |
|---|---|
| MR18R162GAF0-CM8 | (16Mx16)x2(4/8/16)pcs RIMM Module based on 256Mb A-die, 32s banks,16K/32ms Ref, 2.5V |
| MR18R162GAF0-CN9 | Cable; Cable Length:0.33m; Leaded Process Compatible:Yes; No. of Contacts:36; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| MR18R162GAF0-CT9 | (16Mx16)x2(4/8/16)pcs RIMM Module based on 256Mb A-die, 32s banks,16K/32ms Ref, 2.5V |
| MR18R1628AF1-CN9 | (16Mx16)x2(4/8/16)pcs RIMM Module based on 256Mb A-die, 32s banks,16K/32ms Ref, 2.5V |
| MR18R1628AF1-CT9 | (16Mx16)x2(4/8/16)pcs RIMM Module based on 256Mb A-die, 32s banks,16K/32ms Ref, 2.5V |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MR18R1628AF1-CN9 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:(16Mx16)x2(4/8/16)pcs RIMM Module based on 256Mb A-die, 32s banks,16K/32ms Ref, 2.5V |
| MR18R1628AF1-CT9 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:(16Mx16)x2(4/8/16)pcs RIMM Module based on 256Mb A-die, 32s banks,16K/32ms Ref, 2.5V |
| MR18R1628EG0-CK8 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Key Timing Parameters |
| MR18R1628EG0-CM8 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Key Timing Parameters |
| MR18R1628EG0-CM800 | 制造商:Samsung Semiconductor 功能描述:288MRDRAM_MRDRAM MODULEX18WBGA(LF) - Bulk |
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