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參數(shù)資料
| 型號(hào)： | MT55L128L36F1 |
| 廠(chǎng)商： | Micron Technology, Inc. |
| 英文描述： | 3.3V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(3.3V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
| 中文描述： | 3.3V的I / O的128K的× 36，流量通過(guò)ZBT SRAM的電壓（3.3V輸入/輸出，4Mb的流通式同步靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 1/25頁(yè) |
| 文件大小： | 451K |
| 代理商： | MT55L128L36F1 |
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1
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
PRELIMINARY
4Mb
ZBT
SRAM
FEATURES
High frequency and 100 percent bus utilization
Fast cycle times: 10ns, 11ns, and 12ns
Single +3.3V ±5% power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
Advanced control logic for minimum control
signal interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to
eliminate the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or interleaved burst modes
Burst feature (optional)
Pin/function compatibility with 2Mb, 8Mb, and
16Mb ZBT SRAM family
165-pin FBGA package
100-pin TSOP package
Automatic power-down
OPTIONS
Timing (Access/Cycle/MHz)
7.5ns/10ns/100 MHz
8.5ns/11ns/90 MHz
9ns/12ns/83 MHz
Configurations
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
256K x 18
128K x 32
128K x 36
Package
100-pin TQFP
165-pin FBGA
Part Number Example:
MT55L256L18F1T-12
* A Part Marking Guide for the FBGA devices can be found on Micron’s
http://www.micron.com/support/index.html.
MARKING*
-10
-11
-12
MT55L256L18F1
MT55L128L32F1
MT55L128L36F1
MT55L256V18F1
MT55L128V32F1
MT55L128V36F1
T
F
MT55L256L18F1, MT55L128L32F1,
MT55L128L36F1; MT55L256V18F1,
MT55L128V32F1, MT55L128V36F1
3.3V V
DD
, 3.3V or 2.5V I/O
**JEDEC-standard MS-026 BHA (LQFP).
100-Pin TQFP**
165-Pin FBGA
(Preliminary Package Data)
GENERAL DESCRIPTION
The Micron
Zero Bus Turnaround
(ZBT
) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron’s 4Mb ZBT SRAMs integrate a 256K x 18,
128K x 32, or 128K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles when
transitioning from READ to WRITE, or vice versa. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
for easy depth expansion (CE2, CE2#), cycle start input
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT55L128V32F1 | 2.5V I/O， 128K x 32，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
| MT55L128V36F1 | 2.5V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
| MT55L128L32P1 | 3.3V I/O，128K x 32，F(xiàn)low-Through ZBT SRAM(3.3V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
| MT55L128L36P1 | 3.3V I/O，128K x 36，F(xiàn)low-Through ZBT SRAM(3.3V或輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
| MT55L128V32P1 | 2.5V I/O，128K x 32，F(xiàn)low-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L128L36F1-11A | 制造商:Micron Technology Inc 功能描述: |
| MT55L128L36F1F-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L128L36F1T-11 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L128L36P1T-7.5 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT55L128L36P1T-7.5 IT | 制造商:Cypress Semiconductor 功能描述:4MB 128KX36 SRAM PLASTIC IND T |
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