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參數資料
| 型號： | MT5TL8L32T-40IT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 1/31頁 |
| 文件大小： | 584K |
| 代理商： | MT5TL8L32T-40IT |
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PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
MUAC Routing Coprocessor
2002, Micron Technology Inc.
DS-MUAC RCP 8K and 4K.fm - Rev. March/13/02/ 02:20 PM
1
ADVANCE
Melody Routing Coprocessor
MELODY ROUTING
COPROCESSOR (RCP)
FAMILY
4K: MT75L4L32MLQ
8K: MT75L8L32MLQ
For the latest data sheet, please refer to the Micron Web site:
www.micron.com/datasheets
GENERAL DESCRIPTION
The Melody RCP family consists of 4K and 8K x 64-
bit Routing Coprocessors (RCPs) with a 32-bit wide
data interface and a 32-bit ternary compare instruc-
tion. The device is designed for use in layer 3 switches,
routers, and layer 2 switches to provide very high
throughput address translation using tables held in
external RAM. The Melody RCP has a fully determin-
istic search time, independent of the size of the list and
the position of the data in the list. This unique feature
guarantees that the wire speed address recognition
does not impact the latency or induce some jitter on
the latency of the global system. Address fields from
the packet header are compared against a list of entries
stored in the array. As a result of the comparison, the
Melody RCP generates an index that is used to access
an external RAM where port mapping data and other
associated information is stored.
A set of control states provides a powerful and
flexible control interface to the Melody RCP. This
control structure allows memory read and write,
register read and write, data move, comparison,
validity control, addressing control, and initialization
operations.
The Melody RCP architecture uses direct hardware
control of the device and an independent bus for
returning match results. Software control is also
supported for systems where maximum performance is
not needed.
Figure 1. Melody Block Diagram
DQ31–0
VB#
AA Bus
PA3–0
MMI#
RESET#
TCLK
TMS
TDI
TDO
TRST#
PRIORITY
ENCODER
AND
FLAG
LOGIC
E#
CS1#
CS2#
W#
OE#
AV#
AC Bus
DSC#
INSTRUCTION REGISTER
DEVICE SELECT REGISTER
STATUS REGISTER
CONFIGURATION REGISTER
ADDRESS REGISTER
MASK REGISTERS 1–7
COMPARAND REGISTER
4 K x 32 Ternary Word
or
8 K x 32 Ternary Word
Address Database
MF#
MI#
FF#
FI#
CONTROL
AND
ADDRESS
DECODER
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