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參數資料
| 型號： | MT90732 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 61K |
| 代理商： | MT90732 |
5-15
MT90732
E2/E3 Framer (E2/E3F)
Advance Information
Features
Framer for CCITT Recommendations
- G.742 (8448 kbit/s)
- G.745 (8448 kbit/s)
- G.751 (34368 kbit/s)
- G.753 (34368 kbit/s)
Line side interface
- Dual rail or NRZ
HDB3 codec for dual rail I/O
Terminal side interface
- Nibble-parallel
- Bit-serial
Transmit reference generator for bit-serial I/O
Microprocessor or control leads
I/O port for service bits
Applications
Line terminals
Wideband data or video transport
Test equipment
Multiplexer systems
Description
The MT90732 E2/E3 Framer (E2/E3F) is a CMOS
VLSI device that provides the functions needed to
frame a wideband payload to one of four CCITT
Recommendations. G.742, G.745, G.751, or G.753.
The E2/E3 Framer interfaces to line circuitry with
either dual rail or NRZ signals. On the terminal side,
the interface can be either nibble-parallel or bit-
serial.
The MT90732 can be operated with or without a
microprocessor.
When
microprocessor, the E2/E3 Framer provides an 8-
byte memory map for control, performance counters
and alarm status. The MT90732 provides a transmit
and receive interface port for accessing the
overhead
bits
from
recommendations. The overhead bits can also be
accessed by the microprocessor via the memory
map.
interfaced
with
a
each
of
the
four
Ordering Information
MT90732AP 68 Pin PLCC
-40°C to +85°C
Figure 1 - Functional Block Diagram
RP/RDL
RN
RCK/RCKL
CV
TCK/TCKL
TN
RNIB3
RNIB2
RNIB1
RNIB0
RNC
RNF
N.C.
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
SEL
ALE
RD
WR
RDY
XNIB3
XNIB2
XNIB1
XNIB0
XCK
XNF
XNC
TP/TDL
Framer
Interpreter
Output
Micro-
processor
I/O
Input
G.7XX
Send
Line
Encoder
Control
RSD
TDOUT
TCG
TFOUT
RSC
RSF
RCG
N.C.
TCIN
XSD
XCK
N.C.
TCOUT
SERIAL
PARALLEL
XSF
Data
Data
Clock
Frame
Data
Clock
Frame
Data
Clock
Data
Framing
Clock
Clock
Transmit
Reference
Generator
Line
Decoder
RAIS
RLOC
BIP-4E
RLOF
ROD
ROC
ROF
FE
NRZ LINE
BIP-4
M0
M1
MICRO
SER
DAIS
TLBK
PLBK
TAIS
LPT
TLCINV
TLOC
FORCEFE
TOD
TOC
TOF
RESET
TCKL
TDL
RDL
RCKL
Line Side
Terminal Side
ISSUE 1
May 1995
U.S. Patent Number 5040170
CMOS
相關PDF資料 |
PDF描述 |
|---|---|
| MT90733 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90733AP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9074 | T1/E1/J1 Single Chip Transceiver |
| MT9074AL | T1/E1/J1 Single Chip Transceiver |
| MT9074AP | T1/E1/J1 Single Chip Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MT90732AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS E2/E3 Framer (E2/E3F) |
| MT90733 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS DS3 Framer (DS3F) |
| MT90733AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS DS3 Framer (DS3F) |
| MT9074 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver |
| MT9074_05 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver |
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