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參數資料
| 型號： | MTC20136MB-I1 |
| 廠商： | 意法半導體 |
| 英文描述： | ADSL TRANSCEIVER CONTROLLER |
| 中文描述： | 寬帶收發器控制器 |
| 文件頁數： | 19/25頁 |
| 文件大小： | 634K |
| 代理商： | MTC20136MB-I1 |
19/25
MTC20136
Generic Parallel Interface
The two parallel bus modes differ only in the definition of 3 control signals: busmode 0 provides a read/
write selector, a data strobe and a ready acknowledge. Busmode 1 provides a read strobe, a write strobe
and a ready acknowledge. The signal definition is shown in following table:
Table 7. Ctrl-E interface signals in parallel interface modes
Write cycle timing
Figure 8. Ctrl-E interface: write cycle timing in parallel modes 0 and 1
Signal name
C_A[8:0]
C_D[7:0]
C_notCS
C_notInt
Type
I
IO
I
OZ
Function
PIN
address bus
byte wide bidirectional data bus
chip select
Interrupt output, derived from CtrleInt1 signal from
Mailbox : low when CtrleInt1 is low, else tri-stated
C_A[8:0]
C_D[7:0]
C_notCS
C_notInt
Mode 0 : Motorola-compatible mode
C_Mode[1:0]
I
00
b
read access if 1, write access if 0
Data Strobe
Bus cycle ready indication, indicates that data on bus
can be sampled or removed
C_Mode[1:0]
C_Rd/notWr
C_notDS
C_notDtAck
I
I
C_notWr
C_notRd
C_notRdy
OZ
Mode 1 : Intel-compatible mode
C_Mode[1:0]
I
01
b
write cycle indication
read cycle indication
Bus cycle ready indication, indicates that data on bus
can be sampled or removed, same as in mode 0
C_Mode[1:0]
C_notWr
C_notRd
C_notRdy
I
I
C_notWr
C_notRd
C_notRdy
OZ
t1
C_A[8:0]
C_D[7:0]
C_notCS
C_Rd/notWr
C_notDS
C_notDtAck
C_notWr
Mode 0
C_notRd
C_notRdy
t2
t7
t6
t3
t8
t4
t5
t9
Mode 1
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