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參數(shù)資料
型號(hào)： MX88L284AEC
廠商： Electronic Theatre Controls, Inc.
英文描述： Highly integration chip for Flat Panel Display application
中文描述： 高度平板顯示器集成芯片應(yīng)用
文件頁(yè)數(shù)： 1/26頁(yè)
文件大?。?/td> 177K
代理商： MX88L284AEC
MX88L284AEC
Revision: 1.06A
2
Table of Contents
GENERAL DESCRIPTION ...................................................................................................................................4
APPLICATIONS.....................................................................................................................................................4
FEATURES .............................................................................................................................................................4
G
ENERAL
F
EATURES
...............................................................................................................................................4
I
NPUT
.....................................................................................................................................................................5
O
UTPUT
.................................................................................................................................................................5
CPU I
NTERFACE
.....................................................................................................................................................6
M
EMORY
I
NTERFACE
..............................................................................................................................................6
P
OWER
...................................................................................................................................................................6
O
THERS
.................................................................................................................................................................6
CHIP BLOCK DIAGRAM.....................................................................................................................................7
SYSTEM BLOCK DIAGRAM FOR LCD MONITOR (TTL AND PANELLINK/LVDS INTERFACED)........7
SYSTEM DIAGRAM W/O FRAME BUFFER......................................................................................................8
SYSTEM DIAGRAM FOR DIGITAL INPUT INTERFACE ...............................................................................8
PIN CONFIGURATIONS.......................................................................................................................................9
GENERAL DESCRIPTION .................................................................................................................................10
VIP (V
IDEO
I
NPUT
P
ROCESSOR
) F
UNCTION
D
ESCRIPTION
.......................................................................................10
MIU (M
EMORY
I
NTERFACE
U
NIT
) F
UNCTIONAL
D
ESCRIPTION
...............................................................................10
M
EMORY
C
ONFIGURATION
T
ABLE
.........................................................................................................................11
VOP (V
IDEO
O
UTPUT
P
ROCESSOR
) F
UNCTION
D
ESCRIPTION
..................................................................................11
BIU (B
US
I
NTERFACE
U
NIT
) F
UNCTION
D
ESCRIPTION
............................................................................................11
PIN DESCRIPTION..............................................................................................................................................12
CPU I
NTERFACE
P
INS
: (15
PINS
)...........................................................................................................................12
DRAM I
NTERFACE
P
INS
: (52
PINS
) ** 3.3 V
OLT
I
NTERFACE
***..........................................................................12
I
NPUT
I
NTERFACE
P
INS
: (30
PINS
)..........................................................................................................................13
LCD I
NTERFACE
P
INS
: (53
PINS
)...........................................................................................................................13
OSD
INTERFACE
P
INS
: (6
PINS
).............................................................................................................................14
I
NTERNAL
VCG I
NTERFACE
P
INS
: (2
PINS
) ............................................................................................................14
O
THER
I
NTERFACE
P
INS
: (9
PINS
)..........................................................................................................................14
E
XTERNAL
C
LOCK
I
NPUT
I
NTERFACE
P
INS
: (2).....................................................................................................15
P
OWER
P
INS
:........................................................................................................................................................15
AC CHARACTERISTICS....................................................................................................................................16
AC
TIMINGS IF THE LOAD OF ALL OUTPUT PINS IS
5~20
P
F........................................................................................16
1.
I
NPUT SIGNAL
........................................................................................................................................16
2. O
UTPUT SIGNAL
................................................................................................................................................19
E
XTERNAL
OSD
SIGNAL
.......................................................................................................................................20
3. D
IRECT
CPU I
NTERFACE
...................................................................................................................................21
4. S
ERIAL
B
US
I
NTERFACE
.....................................................................................................................................22
5. F
RAME MEMORY
(SDRAM/SGRAM) I
NTERFACE
..............................................................................................23
6. E
XTERNAL
C
LOCK
I
NPUT
I
NTERFACE
.................................................................................................................25
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