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參數(shù)資料
| 型號： | MX88L284AEC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly integration chip for Flat Panel Display application |
| 中文描述： | 高度平板顯示器集成芯片應用 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大小： | 177K |
| 代理商： | MX88L284AEC |
MX88L284AEC
Revision: 1.06A
10
General Description
There are four major parts in this chip which include VIP (Video Input Processor), MIU (Memory
Interface Unit), VOP (Video Output Processor) and BIU (CPU Bus Interface Unit). Following is the block
and description of these parts.
VIP
8/16 bit uP
PC (RGB)/
Video (YUV)
FPD
Panel
OSD
GENERATOR
SDRAM or
SGRAM
VIP LB
MIU
VOP LB
VOP
BIU
Fig. 1 Chip Level Block Diagram
VIP (Video Input Processor) Function Description
VIP is a Video Input Process unit which processes incoming data either from Graphic card or Video
Decoder.
With Line Buffers and Decimation logic based on proprietary Smartscaling
TM
–2 algorithm , it can process
input data and then write to frame buffer . Furthermore, it can detect the polarity of input H/V SYNC and
then do the normalization of them and also detect the ODD/EVEN field of the input interlaced data. It can
also measure the pulse width and period of input H/V SYNC for system application purposes.
Video encoder interface is supported for video image input.
MIU (Memory Interface Unit) Functional Description
MIU is a interface unit between external DRAM and this chip. We support 6 kinds of configurations for
SDRAM and SGRAM through POWER_ON Strapped_Input or register defined value.
DRAM Configuration (Support 8M SGRAM and 16M SDRAM)
DRAM Type
DRAM Number
Bus Width
SGRAM
1
32 bits
SGRAM
2
32 bits
SDRAM
1
16 bits
SDRAM
2
32 bits
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