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參數(shù)資料
| 型號： | NB7L111M |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output(帶有CML輸出的2.5V/3.3V, 6.125Gb/s，1:10差分時鐘/數(shù)據(jù)驅(qū)動器) |
| 中文描述： | 2.5伏/ 3.3伏，6.125Gb / s的1:10差動時鐘/數(shù)據(jù)與CML輸出（帶有白血病輸出的2.5V/3.3V的，6.125Gb /駕駛證，1:10差分時鐘/數(shù)據(jù)驅(qū)動器） |
| 文件頁數(shù)： | 3/13頁 |
| 文件大小： | 257K |
| 代理商： | NB7L111M |
NB7L111M
http://onsemi.com
3
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
15, 24, 27, 39, 42, 51
V
CC
Positive supply voltage. All V
CC
pins must be externally connected to
power supply to guarantee proper operation.
1, 18, 21, 26, 30, 33,
36, 40, 45, 48
V
EE
Negative supply voltage. All V
pins must be externally connected to
power supply to guarantee proper operation.
2
VTCLK0
Internal 50 termination pin for CLK0. (Note 2)
3
CLK0
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Non
inverted differential clock/data input 0 (Note 2).
4
CLK0
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Inverted differential clock/data input 0 (Note 2).
5
VTCLK0
Internal 50 termination pin for CLK0. (Note 2)
6
VTSEL
Internal 50 termination pin for SEL. (Note 2)
7
SEL
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Non
inverted differential clock/data select input. Internal 75 k to V
EE
.
8
SEL
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Inverted differential clock/data select input. Internal 56 K to V
CC
and
56 k to V
EE
bias this pin to (V
CC
V
EE
)/2.
9
VTSEL
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Internal 50 termination pin for SEL. (Note 2)
10
VTCLK1
Internal 50 termination pin for CLK1. (Note 2)
11
CLK1
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Non
inverted differential clock/data input 1 (Note 2).
12
CLK1
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Inverted differential clock/data input 1 (Note 2).
13
VTCLK1
Internal 50 termination pin for CLK1. (Note 2)
14, 25, 41, 52
NC
17, 20, 23, 29, 32, 35,
38, 44, 47, 50
Q[0
9]
CML Outputs
Non
inverted CML outputs [0
9] with internal 50 source termination
resistor (Note 1).
16, 19, 22, 28, 31, 34,
37, 43, 46, 49
Q[0
9]
CML Outputs
Inverted CML outputs [0
9] with internal 50 source termination
resistor (Note 1).
EP
Exposed Pad (EP). The thermally exposed pad on package bottom (see
case drawing) must be attached to a heat
sinking conduit on the printed
circuit board.
1. CML output requires 50 receiver termination resistor to V
CC
for proper operation.
2. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK then the device will be susceptible to self
oscillation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB7L111MMN | 功能描述:時鐘驅(qū)動器及分配 2.5V/3.3V 6.125Gb/s RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| NB7L111MMNG | 功能描述:時鐘驅(qū)動器及分配 2.5V/3.3V 6.125Gb/s 1:10 Clk/Data Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| NB7L111MMNR2 | 功能描述:時鐘驅(qū)動器及分配 2.5V/3.3V 6.125Gb/s RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| NB7L111MMNR2G | 功能描述:時鐘驅(qū)動器及分配 2.5V/3.3V 6.125Gb/s 1:10 Clk/Data Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| NB7L11M | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination |
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