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參數資料
型號: NB7V58MMNTXG
廠商: ON Semiconductor
文件頁數: 1/8頁
文件大小: 0K
描述: IC CLOCK/DATA MUX 2:1 7GHZ 16QFN
標準包裝: 3,000
系列: GigaComm™
類型: 多路復用器,數據
電路數: 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: CML
頻率 - 最大: 7GHz
電源電壓: 1.71 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應商設備封裝: 16-QFN(3x3)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2009
August, 2009 Rev. 0
1
Publication Order Number:
NB7V58M/D
NB7V58M
1.8 V / 2.5 V / 3.3 V
Differential 2:1 Clock / Data
Multiplexer / Translator
with CML Outputs
MultiLevel Inputs w/ Internal
Termination
Description
The NB7V58M is a high performance differential 2to1 Clock or
Data multiplexer. The differential inputs incorporate internal 50
W
termination resistors that are accessed through the VT pin. This
feature allows the NB7V58M to accept various logic level standards,
such as LVPECL, CML or LVDS.
The NB7V58M produces minimal Clock or Data jitter operating up
to 7 GHz or 10.7 Gb/s, respectively. As such, the NB7V58M is ideal
for SONET, GigE, Fiber Channel, Backplane and other Clock/Data
distribution applications.
The 16 mA differential CML outputs provide matching internal
50
W terminations and 400 mV output swings when externally
terminated with a 50
W resistor to VCC.
The NB7V58M is offered in a low profile 3 mm x 3 mm 16pin
QFN package and is a member of the GigaComm
t family of high
performance Clock / Data products. For applications that require
equalization, the pincompatible NB7VQ58M is also available.
Application notes, models, and support documentation are available at
Features
Maximum Input Data Rate > 10.7 Gb/s
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 7 GHz
Random Clock Jitter < 0.8 ps RMS
180 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV PeaktoPeak, Typical
Operating Range: VCC = 1.71 V to 3.6 V with GND = 0 V
Internal 50 W Input Termination Resistors
QFN16 Package, 3 mm x 3 mm
40°C to +85°C Ambient Operating Temperature
This is a PbFree Device
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
16
NB7V
58M
ALYW G
G
1
SIMPLIFIED BLOCK DIAGRAM
(Note: Microdot may be in either location)
1
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