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參數資料
| 型號： | OR3LP26B |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable System Chip，Embedded Master/Target PCI Bus Interface(現場可編程系統芯片，嵌入式主機/從機PCI總線接口) |
| 中文描述： | 現場可編程系統芯片，嵌入式主/ PCI總線目標接口（現場可編程系統芯片，嵌入式主機/從機的PCI總線接口） |
| 文件頁數： | 1/6頁 |
| 文件大小： | 151K |
| 代理商： | OR3LP26B |
Preliminary Product Brief
September 1999
ORCA
OR3LP26B Field-Programmable System Chip (FPSC)
Embedded Master/Target PCI Bus Interface
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of an FPGA-based design imple-
mentation, coupled with the high bandwidth of an
industry-standard PCI interface. The ORCA
OR3LP26B, a member of the Series 3+ FPSC family,
provides a full-featured 33/50/66 MHz, 32-/64-bit PCI
interface, fully designed and tested, in hardware, plus
FPGA logic for user-programmable functions.
PCI Bus Core Highlights
I
Implemented in an ORCA Series 3 OR3L125B
base array, displacing the bottom ten rows of 28
columns.
I
Core is a well-tested ASIC model.
I
Fully compliant to Revision 2.2 of PCI Local Bus
Specification.
I
Operates at PCI bus speeds up to 66 MHz on a
32-/64-bit wide bus.
I
Comprises two independent controllers for Master
and Target.
I
Meets/exceeds all requirements for PICMG
*
Hot
Swap Friendly silicon, Full Hot Swap model, per
the CompactPCI
*
Hot Swap Specification, PICMG
2.1 R1.0.
I
PCI SIG Hot Plug (R1.0) compliant.
I
Four internal FIFOs individually buffer both direc-
tions of both the Master and Target interfaces:
— Both Master FIFOs are 64 bits wide by 32 bits
deep.
— Both Target FIFOs are 64 bits wide by 16 bits
deep.
I
Capable of no-wait-state, full-burst PCI transfers in
either direction, on either the Master or Target
interface. The dual 64-bit data paths extend into
the FPGA logic, permitting full-bandwidth, simulta-
neous bidirectional data transfers of up to
528 Mbytes/s to be sustained indefinitely.
I
Can be configured to provide either two 64-bit
buses (one in each direction) to be multiplexed
between Master and Target, or four independent
32-bit buses.
I
Provides many hardware options in the PCI core
that are set during FPGA logic configuration.
I
Operates within the requirements of the PCI 5 V
and 3.3 V signaling environments and 3.3 V com-
mercial or industrial environmental conditions,
allowing the same device to be used in 5 V or 3.3 V
PCI systems.
*
PICMG and CompactPCI are registered trademarks of the PCI
Industrial Computer Manufacturers Group.
Table 1. ORCA OR3LP26B PCI FPSC Solution—Available FPGA Logic
The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable
gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only
gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12
gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic,
CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4
RAM (or 512 gates) per PFU.
Device
Usable Gates
Number of
LUTs
4032
Number of
Registers
5304
Max User
RAM
64K
Max User
I/Os
259
Array
Size
18 x 28
Number of
PFUs
504
OR3LP26B
60K—120K
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相關代理商/技術參數 |
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|---|---|
| OR3LP26BBA352-DB | 功能描述:FPGA - 現場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3LP26BBM680-DB | 功能描述:FPGA - 現場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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