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參數資料
| 型號： | P14827EJ1V0AN00 |
| 英文描述： | uPB1005K RF/IF Down-Converter+PLL Frequency Synthesizer ICs for GPS Receivers |
| 中文描述： | uPB1005K射頻/中頻下變頻器鎖相環頻率合成器的GPS接收機 |
| 文件頁數： | 9/23頁 |
| 文件大小： | 188K |
| 代理商： | P14827EJ1V0AN00 |
Preliminary Application Note P14822EJ2V0AN
9
4. EXTERNAL CIRCUIT CONFIGURATIONS
4.1 Impedance Matching at RF Output
Since this IC has an open-collector output, configure an LC matching circuit for RF impedance using an external
component. The matching circuit should include a parallel inductor to the V
CC
side and a series capacitor toward the
next stage. As mentioned earlier, the bias of the output pin's collector uses the method applying the V
CC
pin's voltage
via the inductor used for RF matching. In other words, the inductor that is connected to the output pin has two effects:
its RF effect (frequency matching) and its DC effect (application of bias). This is why a small DC resistance and high-
frequency type inductor should be used.
The LC matching circuit constants used in the test circuits shown in the data sheet are for the NEC evaluation
board. This evaluation board is used only for simple evaluations; devices evaluated using this board are not
immediately suitable for application in systems. The patterns used for evaluation does not allow parts to be mounted
near the IC, so the pattern size is larger. Accordingly, these are not the recommended patterns or the recommended
circuit constants.
The matching LC value is determined so as to produce narrow-band power gain that suits the used frequency
bandwidth referencing the IC's own S-parameters. Select a value that reduces the S
22
value of the RF output pin to
about
20 dBm during maximum gain within the used frequency bandwidth. Examples of RF matching circuit
configurations are the high-pass type at 900 MHz and the low-pass type at 1.9 GHz and 2.4 GHz. Figure 4-1 shows
examples of external circuit configurations.
4.2 Input Impedance Matching
The IF and LO inputs in this IC are base inputs with parallel connections to bias resistors. Although their
characteristic impedance is not 50
, the test circuits in the data sheet show a signal generator with a 50
signal
source impedance. Accordingly, the data sheet's electrical specifications include loss due to this mismatched
impedance. If impedance matching is implemented in the actual circuit, the elimination of this loss raises the IC's
input level, which lowers the required input level.
Figure 4-2 shows S parameter values for the RF, IF, and LO ports when matching is not implemented.
4.3 Bypass Capacitor
Like other ICs, this IC needs an RF bypass to GND for its V
CC
pin, so an external capacitor should be connected to
the V
CC
pin as the bypass.
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