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參數(shù)資料
| 型號(hào)： | P82C150AHT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 22 PIN R/A MALE PRESSFIT ATCA ZONE 1 CON |
| 中文描述： | 1 CHANNEL(S), 125K bps, LOCAL AREA NETWORK CONTROLLER, PDSO28 |
| 封裝： | 7.50 MM, PLASTIC, SO-28 |
| 文件頁數(shù)： | 24/36頁 |
| 文件大小： | 209K |
| 代理商： | P82C150AHT |
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1996 Jun 19
24
Philips Semiconductors
Preliminary specification
CAN Serial Linked I/O device (SLIO) with
digital and analog port functions
P82C150
Notes to the DC characteristics:
1.
Alteration of V
DD
between two calibration messages should not exceed 0.2 V to avoid failures during CAN
message transfer. If CAN devices according to CAN specification V1.0 or V1.1 (like the 82C200 V0 or V1) are in the
same network with the 82C150, then this alteration of V
DD
should be limited to 0.1V for the 82C150.
2.
These values are characterized but not 100% production tested.
3.
The TX0 output pin is an open drain pull-down driver (no pull-up driver included).
4.
The TX1 output pin is an open drain pull-up driver (no pull-down driver included).
10 AC CHARACTERISTICS
V
DD
= 5 V
±
4%; V
SS
= 0 V; C
L
= 100 pF (output pins); T
amb
=
40 to +85
°
C and T
amb
=
40 to +125
°
C; unless
otherwise specified.
Notes
1.
2.
Other bit time values are possible with the external oscillator mode (refer to Chapter 11.3).
These values are characterized but not 100% production tested.
OC1 comparator input P15
V
i sw
input switch-over voltage
lower threshold
upper threshold
input leakage current
analog input capacitance
1.5 V < V
I
< (AV
DD
1.5 V);
note 2
0.5V
DD
0.02
V
V
nA
pF
0.5V
DD
+ 0.02
±
400
20
I
LI2
C
IA
Analog switches; ION =
±
4 mA
R
ON
On resistance
0.45 V < V
I
< V
DD
0.45 V
note 2
between P5 to P9, P13 and
P14; note 2
20
200
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
f
CLK_INT
t
bit
t
RST1
t
RST2
t
hold
t
d
system clock frequency on-chip
bit time on CAN-bus
min. RST pulse width after power on
min. RST pulse width during operation
ID hold time after end of reset
total signal delay of CAN input comparator and
CAN output driver
max. time without recalibration message
internal oscillator
note 1
note 2
note 2
note 2
0.3AV
DD
< V
I
< 0.7AV
DD
;
note 2
4
8
150
1
100
10
50
100
MHz
μ
s
ms
μ
s
ns
ns
t
rep
8000
bit
Analog-to-digital comparator input P15
t
cyc
t
init
analog-to-digital conversion cycle time
initialization time of analog-to-digital conversion
0.4
0.4
1.1
2.1
ms
ms
OC2 comparator P12, P13 and OC3 comparator P10, P11
t
resp
response time
V
DIF1
=
±
100 mV; note 2
1
μ
s
DPM1 and DPM2 outputs
t
DPM
repetition time of DPM cycle
0.4
1.1
ms
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
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