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參數資料
| 型號： | P89LPC922 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | MINIATURE POWER RELAY |
| 中文描述： | 8位微控制器兩個小時80C51的核心2鍵盤/ 4 KB的/ 8 KB的3伏的低功耗Flash 256 - RAM的字節數據 |
| 文件頁數： | 36/45頁 |
| 文件大小： | 877K |
| 代理商： | P89LPC922 |
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Philips Semiconductors
P89LPC920/921/922
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 06 — 21 November 2003
36 of 45
9397 750 12285
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[2]
The I
DD
, I
ID
, and I
PD
specifications are measured using an external clock with the following functions disabled: comparators, brownout
detect, and Watchdog timer.
See
Table 7 “Limiting values” on page 34
for steady state (non-transient) limits on I
OL
or I
OH
. If I
OL
/I
OH
exceeds the test condition,
V
OL
/V
OH
may exceed the related specification.
Pin capacitance is characterized but not tested.
Measured with port in quasi-bidirectional mode.
Measured with port in high-impedance mode.
Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). Does not apply to open-drain pins.
Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest
when V
IN
is approximately 2 V.
[3]
[4]
[5]
[6]
[7]
[8]
11. Dynamic characteristics
[1]
[2]
Parameters are valid over operating temperature range unless otherwise specified.
Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
Table 9:
T
amb
=
40
°
C to +85
°
C for industrial, unless otherwise specified.
[1]
Symbol
Parameter
AC characteristics
Conditions
Variable clock
Min
7.189
f
OSC
= 12 MHz
Min
7.189
Unit
Max
7.557
Max
7.557
f
RCOSC
internal RC oscillator frequency
(nominal f = 7.3728 MHz)
internal Watchdog oscillator
frequency (nominal f = 400 kHz)
oscillator frequency
clock cycle
CLKLP active frequency
Glitch filter
glitch rejection, P1.5/RST pin
signal acceptance, P1.5/RST pin
glitch rejection, any pin except
P1.5/RST
signal acceptance, any pin except
P1.5/RST
External clock
t
CHCX
HIGH time
t
CLCX
LOW time
t
CLCH
rise time
t
CHCL
fall time
Shift register (UART mode 0)
t
XLXL
serial port clock cycle time
t
QVXH
output data set-up to clock rising
edge
t
XHQX
output data hold after clock rising
edge
t
XHDX
input data hold after clock rising edge
t
DVXH
input data valid to clock rising edge
trimmed to
±
1%
at T
amb
= 25
°
C
MHz
f
WDOSC
280
480
280
480
kHz
f
OCS
t
CLCL
f
CLKP
0
83
0
12
-
8
-
-
-
-
-
-
MHz
ns
MHz
see
Figure 13
-
125
-
50
-
15
-
125
-
50
-
15
ns
ns
ns
50
-
50
-
ns
see
Figure 13
see
Figure 13
see
Figure 13
see
Figure 13
33
33
-
-
t
CLCL
t
CLCX
t
CLCL
t
CHCX
8
8
33
33
-
-
-
-
8
8
ns
ns
ns
ns
16 t
CLCL
13 t
CLCL
-
-
1333
1083
-
-
ns
ns
-
t
CLCL
+ 20
-
103
ns
-
150
0
-
-
150
0
-
ns
ns
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