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參數資料
| 型號： | PA7536SI-15 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數： | 2/10頁 |
| 文件大小： | 219K |
| 代理商： | PA7536SI-15 |
2
04-02-052D
Commercial/Industrial
Inside the Logic Array
The heart of the PEEL
Array architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. Depending on the PEEL
Array selected, a
range of 38 to 62 inputs is available into the array from the
I/O cells, inputs cells and input/global-clock pins.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
number of product-terms among PEEL
Arrays ranges
from 67 to 125. All product terms (with the exception of
certain ones fed to the global cells) can be programmably
connected to any of the sum-terms of the logic control cells
(four sum-terms per logic control cell). Product-terms and
sum-terms are also routed to the global cells for control
purposes. Figure 3 shows a detailed view of the logic
array structure.
From
IO Cells
(IOC,INC,
I/CLK)
From
Logic
Control
Cells
(LCC)
To
Global
Cells
38 Array Inputs
67 Product Terms
To
Logic Control
Cells
(LCC)
50 Sum Terms
PA7536 Logic Array
08-16-003A
Figure 3 PA7536 Logic Array
True Product-Term Sharing
The PEEL
logic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as
commonly found in other CPLDs. Product term sharing
ensures that product-terms are used where they are
needed and not left unutilized or duplicated. Secondly, the
sum-of-products functions provided to the logic cells can
be used for clocks, resets, presets and output enables
instead of just simple product-term control.
The PEEL
logic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product
terms to implement 16 exclusive-OR functions. The
PEEL
logic array easily handles this in a single level
delay. Other PLDs/CPLDs either run out of product-terms
or require expanders or additional logic levels that often
slow performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control
the logic functions created in the logic array. Each LCC has
four primary inputs and three outputs. The inputs to each
LCC are complete sum-of-product logic functions from the
array, which can be used to implement combinatorial and
sequential logic functions, and to control LCC registers and
I/O cell output enables.
A
B
C
D
REG
D,T,J
K
R
P
Q
MUX
System Clock
Preset
Reset
On/Off
RegType
From Global Cell
MUX
MUX
To
Array
To
I/O
Cell
From
Array
08-16-004A
Figure 4. Logic Control Cell Block Diagram
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with
synchronous or asynchronous D, T, or JK registers
(clocked-SR registers, which are a subset of JK, are also
possible). See Figure 5. EEPROM memory cells are used
for programming the desired configuration. Four sum-of-
product logic functions (SUM terms A, B, C and D) are fed
into each LCC from the logic array. Each SUM term can be
selectively used for multiple functions as listed below.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PA7536SI-15L | 功能描述:SPLD - 簡單可編程邏輯器件 14 Input 12 I/O 15ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PA7536T-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| PA7536TI-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| PA7540 | 制造商:ANACHIP 制造商全稱:Anachip Corp 功能描述:PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
| PA7540J-15 | 功能描述:EEPLD - 電子擦除可編程邏輯設備 2 INP 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數:8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-20 |
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