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參數資料
| 型號： | PA7536T-15 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 219K |
| 代理商： | PA7536T-15 |
1
04-02-052D
Commercial/Industrial
PA7536 PEEL Array
Programmable Electrically Erasable Logic Array
Versatile Logic Array Architecture
- 12 I/Os, 14 inputs, 36 registers/latches
- Up to 36 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and
other wide-gate functions
High-Speed Commercial and Industrial Versions
- As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (f
MAX
)
- Industrial grade available for 4.5 to 5.5V V
CC
and
-40 to +85 °C temperatures
General Description
The PA7536 is a member of the Programmable Electrically
Erasable Logic (PEEL) Array family based on ICT’s
CMOS EEPROM technology. PEEL Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7536 offers
versatile logic array architecture with 12 I/O pins, 14 input
pins and 36 registers/latches (12 buried logic cells, 12
Input registers/latches and 12 buried registers/latches). Its
logic array implements 50 sum-of-products logic functions
that share 64 product terms. The PA7536’s logic and I/O
cells (LCCs, IOCs) are extremely flexible offering up to
three output functions per cell (a total of 36 for all 12 logic
cells). Cells are configurable as D, T, and JK registers with
Figure 1. Pin Configuration
CMOS Electrically Erasable Technology
- Reprogrammable in 28-pin DIP, SOIC and PLCC
packages
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- ICT WinPLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmer
independent or global clocks, resets, presets, clock
polarity, and other special features, making the PA7536
suitable for a variety of combinatorial, synchronous and
asynchronous logic applications. The PA7536 offers pin
compatibility and super-set functionality to popular 28-pin
PLDs, such as the 26V12. Thus, designs that exceed the
architectures of such devices can be expanded upon. The
PA7536 supports speeds as fast as 9ns/15ns (tpdi/tpdx)
and 83.3MHz (f
MAX
) and moderate power consumption
60mA (45mA typical). Packaging includes 28-pin DIP,
SOIC, and PLCC (see Figure 1). Development and
programming support for the PA7536 is provided by ICT
and popular third-party development tool manufacturers.
08-16-001A
DIP
I/CLK1
1
I
2
I
3
I
4
I
5
I
6
VCC
7
I
8
I
9
I
10
I
11
I
12
I/O
24
I/O
23
I/O
22
GND
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I
13
I
14
I/CLK2
28
I/O
27
I/O
26
I/O
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
I/CLK1
I
I
I
I
I
VCC
I
I
I
I
I
I
I
24
23
22
21
20
19
18
17
16
15
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
SOIC/TSSOP
28
27
26
25
I/CLK2
I/O
I/O
I/O
PLCC
25
I/O
24
I/O
23
I/O
22
I/O
21
GND
20
I/O
19
I/O
4
I
3
I
2
I
1
I
28
I
27
I
26
I
5
I
6
I
7
VCC
8
I
9
I
10
I
11
I
12
I
13
I
14
I
15
I
16
I
17
I
18
I
Figure 2. Block Diagram
Input
Cells
(INC)
12 Input Pins
2 Input/
Global Clock Pins
Global
Cells
2
12
I/O
Cells
(IOC)
Logic
Control
Cells
(LCC)
12
12
12
12
A
B
C
D
76 (38X2)
Array Inputs
true and
complement
Buried
logic
2 sum terms
3 product terms
for Global Cells
12 Logic Control Cells
up to 3 output functions per cell
(36 total output functions possible)
Logic functions
to I/O cells
12 I/O Pins
48 sum terms
(four per LCC)
Logic
Array
08-16-002A
PA7536
I
I
I
I
I
VCC
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/CLK2
I/CLK1
I
I
I/O
I/O
I/O
Global Cells
Input Cells
I/O Cells
I
I/O
I/O
I/O
Logic Control Cells
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PA7536TI-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| PA7540 | 制造商:ANACHIP 制造商全稱:Anachip Corp 功能描述:PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
| PA7540J-15 | 功能描述:EEPLD - 電子擦除可編程邏輯設備 2 INP 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數:8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-20 |
| PA7540J-15L | 功能描述:EEPLD - 電子擦除可編程邏輯設備 2 INP 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數:8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-20 |
| PA7540JI-15 | 功能描述:EEPLD - 電子擦除可編程邏輯設備 2 INP 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數:8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-20 |
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