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參數(shù)資料
| 型號(hào)： | PCA3354CH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 14 X 14 X 2.20 MM, PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 14/32頁(yè) |
| 文件大小： | 221K |
| 代理商： | PCA3354CH |
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1996 Dec 18
14
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF
generator and 256 bytes EEPROM
PCA3354C; PCD3354A
7.1.2
EEPROM
ADDRESS REGISTER
(ADDR)
The EEPROM Address Register determines the EEPROM location to which an EEPROM access is directed.
As a whole, ADDR auto-increments after read and write cycles to EEPROM, but remains fixed after erase cycles. This
behaviour generates the correct ADDR contents for sequential read accesses and for sequential write or erase/write
accesses with intermediate page setup. Overflow of the 8-bit counter wraps around to zero.
Table 13
EEPROM Address Register (address 01H, access type R/W)
Table 14
Description of ADDR bits
7.1.3
EEPROM D
ATA
R
EGISTER
(DATR)
Table 15
EEPROM Data Register (address 03H; access type R/W)
Table 16
Description of DATR bits
7.1.4
EEPROM
TEST REGISTER
(TST)
The EEPROM Test register is used for testing purposes during device manufacture. It must not be accessed by the
device user.
7
6
5
4
3
2
1
0
0
AD6
AD5
AD4
AD3
AD2
AD1
AD0
BIT
SYMBOL
AD6 to AD2
AD1 to AD0
DESCRIPTION
7
This bit is set to a logic 0.
AD2 to AD6 select one of 32 pages.
AD1 and AD0 are irrelevant during erase and write cycles. For read accesses, AD0 and
AD1 indicate the byte location within an EEPROM page. During page setup, finally, AD0
and AD1 select EEPROM Latch 0 to 3 whereas AD2 to AD6 are irrelevant. If increment
mode (Table 12) is active during page setup, the subcounter consisting of AD0 and AD1
increments after every write to an EEPROM latch, thus enhancing access to sequential
EEPROM latches. Incrementing stops when EEPROM Latch 3 is reached, i.e. when
AD0 and AD1 are both a logic 1.
6 to 2
1 to 0
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
BIT
SYMBOL
DESCRIPTION
7 to 0
D7 to D0
The EEPROM Data Register (DATR) is only a conceptual entity. A read operation from
DATR, reads out the EEPROM byte addressed by ADDR. On the other hand, a write
operation to DATR, loads data into the EEPROM latch (see Fig.4) defined by bits AD0
and AD1 of ADDR.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCD3354A | 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM |
| PCA3354C | 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM |
| PCD3359A | 8-bit microcontroller with DTMF generator and 128 bytes EEPROM |
| PCD3359AH | 8-bit microcontroller with DTMF generator and 128 bytes EEPROM |
| PCD3359AP | 8-bit microcontroller with DTMF generator and 128 bytes EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCA36-0 | 制造商:Panduit Corp 功能描述:B-ID |
| PCA36-1 | 制造商:Panduit Corp 功能描述:B-ID |
| PCA-36-2 | 制造商:Panduit Corp 功能描述: |
| PCA36-2 | 制造商:Panduit Corp 功能描述: |
| PCA36-3 | 制造商:Panduit Corp 功能描述: |
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