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參數資料
| 型號： | PCD3312CP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | DTMF/modem/musical-tone generators |
| 中文描述： | TELEPHONE MULTIFUNCTION CKT, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, SOT97-1, DIP-8 |
| 文件頁數： | 14/28頁 |
| 文件大小： | 176K |
| 代理商： | PCD3312CP |
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1996 Nov 21
14
Philips Semiconductors
Product specification
DTMF/modem/musical-tone generators
PCD3311C; PCD3312C
Table 6
Explanation of time symbols used in Fig.11
8.5.2
L
OW
-
SPEED MODE
Masters generate a bus clock with a maximum frequency of 2 kHz; a minimum LOW period of 105
μ
s and a minimum
HIGH period of 365
μ
s. The mark-to-space ratio is 1 : 3 LOW-to-HIGH. Detailed timing is shown in Fig.13, where the two
signal levels are LOW = V
IL
and HIGH = V
IH
, see Chapter 11. Figure 14 shows a complete data transfer in low-speed
mode.The time symbols are explained in Table 7.
SYMBOL
PARAMETER
REMARKS
MIN.
MAX.
UNIT
f
SCL
t
SW
t
BUF
SCL clock frequency
tolerable pulse spike width
bus free time
0
4.7
100
100
kHz
ns
μ
s
The time that the bus is free (SDA is HIGH)
before a new transmission is initiated by SDA
going LOW.
Only valid for repeated start code.
The time between SDA going LOW and the first
valid negative-going transition of SCL.
The LOW period of the SCL clock.
The HIGH period of the SCL clock.
t
SU;STA
t
HD;STA
set-up time repeated START
hold time START condition
4.7
4.0
μ
s
μ
s
t
LOW
t
HIGH
t
r
t
f
t
SU;DAT
t
HD;DAT
t
SU;STO
SCL LOW time
SCL HIGH time
rise time SDA and SCL
fall time SDA and SCL
data set-up time
data hold time
set-up time STOP condition
4.7
4.0
250
0
4.0
1.0
0.3
μ
s
μ
s
μ
s
μ
s
ns
ns
μ
s
Fig.12 Complete data transfer in standard mode.
handbook, full pagewidth
MBC765
9
8
1 - 7
9
8
1 - 7
9
8
1 - 7
STOP
ACK
ADDRESS
R/W
START
CONDITION
ACK
DATA
START
CONDITION
ACK
ADDRESS
R/W
SCL
Clock LOW minimum = 4.7
μ
s; clock HIGH minimum = 4
μ
s.
The dashed line is the acknowledgment of the receiver.
Mark-to-space ratio = 1 : 1 (LOW-to-HIGH).
Maximum number of bytes is unrestricted.
Premature termination of transfer is allowed by generation of STOP condition.
Acknowledge clock bit must be provided by master.
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