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參數資料
| 型號： | PCD5003A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Enhanced Pager Decoder for POCSAG |
| 中文描述： | 增強傳呼機POCSAG碼解碼器 |
| 文件頁數： | 13/44頁 |
| 文件大小： | 233K |
| 代理商： | PCD5003A |
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1999 Jan 08
13
Philips Semiconductors
Product specification
Enhanced Pager Decoder for POCSAG
PCD5003A
Table 9
Call terminator bit identification
Note
1.
The DF bit in the call terminator is set:
a) When any call data code-word in the terminating batch was uncorrectable, while in ‘data receive’ mode.
b) When the sync word at the start of the terminating batch did not match the standard POCSAG or a
user-programmed sync word, while in ‘data fail’ mode.
Table 10
Error type identification (note 1)
Note
1.
POCSAG code allows a maximum of three bit errors to be detected per code-word.
BITS (MSB TO LSB)
IDENTIFICATION
FT
forced call termination (1 = yes)
identifier number of last sync word
data fail mode indication (1 = data fail mode); note 1
detected error type; see Table 10; E3 = 0 in a call terminator
S3 to S1
DF
E3 to E1
E3
E2
E1
ERROR TYPE
NUMBER OF ERRORS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
no errors; correct code-word
parity bit in error
single bit error
single bit error and parity error
not used
4-bit burst error and parity error
2-bit random error
uncorrectable code-word
0
1
1 + parity
1
3 (e.g. 1101)
2
3 or more
Call termination can occur on reception of an address
code-word (or even a message code-word if in enhanced
call termination mode) or when a sync word is not detected
while in the ‘data fail’ mode.
7.19
Receiver and oscillator control
A paging receiver and an RF oscillator circuit can be
controlled independently via enable outputs RXE and ROE
respectively. Their operating periods are optimized
according to the synchronization mode of the decoder.
Each enable signal has its own programmable
establishment time (see Table 11).
7.20
External receiver control and monitoring
An external controller may enable the receiver control
outputs continuously via an I
2
C-bus command, overruling
the normal enable pattern. Data reception continues
normally. This mode can be left by means of a reset or an
I
2
C-bus command.
External monitoring of the receiver control output RXE is
possible via bit D6 in the status register, when enabled via
the control register (D2 = 1). Each change of state of
output RXE will generate an external interrupt at output
INT.
相關PDF資料 |
PDF描述 |
|---|---|
| PCD5003AH | Enhanced Pager Decoder for POCSAG |
| PCD5003 | Advanced POCSAG Paging Decoder |
| PCD5003H | Advanced POCSAG Paging Decoder |
| PCD5008 | FLEX Pager Decoder |
| PCD5008H | FLEX Pager Decoder |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PCD5003AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG |
| PCD5003H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5003HB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5003U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5008 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:FLEX Pager Decoder |
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