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參數資料
| 型號： | PCD5096 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | Universal codec |
| 中文描述： | 通用編解碼器 |
| 文件頁數： | 15/52頁 |
| 文件大?。?/td> | 222K |
| 代理商： | PCD5096 |
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1997 Jan 22
15
Philips Semiconductors
Preliminary specification
Universal codec
PCD5096
8.3.4
C
ONTROL
R
EGISTER
2 (CR2)
CR2 contains the gain setting values of the analog Codec 1 and Codec 2 section. The state of CR2 after reset is 0000H.
This sets the A/D path and the D/A path gain to their minimum values of +9 dB and
13 dB respectively.
The D/A path gain is defined as the relationship between the level of the analog output signal, differentially seen at
EARP_HS - EARM_HS or LIFP_DA1 - LIFM_DA1, expressed in dBm (0 dBm0 is 1 mW in 600
), and the level of the
digital input signal at the PCM interface, expressed in dBm0 according to CCITT Recommendation G.711. This D/A path
gain definition assumes that the volume control in the DSP is set to the default value of 0 dB.
The A/D path gain is defined as the relationship between the level of the digital output signal at the PCM interface,
expressed in dBm0, and the level of the analog input signal at the LIF interface, differentially seen at
LIFP_AD2 - LIFM_AD2 or LIFP_AD1 - LIFM_AD1, expressed in dBm.
Table 11
Control Register 2 (address 7AH)
Table 12
Control Register 2 (continued)
Table 13
Description of CR2 bits
15
14
13
12
11
10
9
8
DA2.3
DA2.2
DA2.1
DA2.0
AD2.3
AD2.2
AD2.1
AD2.0
7
6
5
4
3
2
1
0
DA1.3
DA1.2
DA1.1
DA1.0
AD1.3
AD1.2
AD1.1
AD1.0
BIT
SYMBOL
DESCRIPTION
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DA2.3
DA2.2
DA2.1
DA2.0
AD2.3
AD2.2
AD2.1
AD2.0
DA1.3
DA1.2
DA1.1
DA1.0
AD1.3
AD1.2
AD1.1
AD1.0
These 4 bits select the D/A path gain for Codec 2; see Table 14.
These 4 bits select the A/D path gain for Codec 2; see Table 15.
These 4 bits select the D/A path gain for Codec 1; see Table 14.
These 4 bits select the A/D path gain for Codec 1; see Table 15.
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相關代理商/技術參數 |
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