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參數(shù)資料
| 型號： | PCD5096 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | Codec |
| 英文描述： | Universal codec |
| 中文描述： | 通用編解碼器 |
| 文件頁數(shù)： | 43/52頁 |
| 文件大小： | 222K |
| 代理商： | PCD5096 |
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1997 Jan 22
43
Philips Semiconductors
Preliminary specification
Universal codec
PCD5096
16 ELECTRICAL SPECIFICATIONS
Table 44
General parameters
Notes
1.
V
DD_1
supplies all digital I/Os to ensure 5 V interfacing. V
DD_1
may vary over its range independent of the value of
V
DD_2
, V
DDA_1
, V
DDA_2
and V
DD_PLL
. If V
DD_1
is 5.5 V, V
DD_2
cannot be lower than 3.0 V.
I
DD_1(act)
is application dependent.
Power off at 25
°
C and 3.3 V, RESET pin HIGH, clock not running. The pins IO0 and IO1 are then inputs and must
be kept HIGH (internal pull-ups).
V
DD_2
, V
DDA_1
, V
DDA_2
and V
DD_PLL
will have the same value. Internally they are NOT connected.
Active mode at 25
°
C and 3.3 V, clock running. DSP parameter table, IOM control table and control registers set
according to Section 13.1 (application example with two active channels). A sine wave signal (1031.25 Hz) at a level
of
25 dBm is applied to the microphone input of both codecs. DI is tied to DO to simulate activity on the IOM-2
interface.
No load on LIFM_DA1, LIFP_DA1, EARM_HS, EARP_HS, VBGP, VREF1, VREF2, VMIC_HS and VMIC_HF.
2.
3.
4.
5.
6.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
f
clk
T
amb
V
DD_1
I
DD_1(act)
I
DD_1(off)
V
DD_2
I
DD_2(act)
I
DD_2(off)
V
DDA_1
I
DDA_1(act)
I
DDA_1(off)
V
DDA_2
I
DDA_2(act)
I
DDA_2(off)
V
DD_PLL
I
DD_PLL(act)
I
DD_PLL(off)
I
DD(tot)(off)
clock frequency
ambient temperature
supply voltage
active supply current
power off supply current
supply voltage
active supply current
power off supply current
analog supply voltage
active analog supply current
power off supply current
analog supply voltage
active analog supply current
power off supply current
supply voltage
active supply current
power off supply current
total power off supply current
25
2.7
2.7
2.7
6.912
+25
3.3
0.1
3.3
18
4
3.3
1.5
33
3.3
1.5
2
3.3
0.1
1
40
+70
5.5
3.6
28
3.6
3
3.6
3
3.6
1
70
MHz
°
C
V
mA
μ
A
V
mA
μ
A
V
mA
μ
A
V
mA
μ
A
V
mA
μ
A
μ
A
note 1
note 2
note 3
note 4
note 5
note 3
note 4
no load; notes 5 and 6
note 3
note 4
no load; notes 5 and 6
note 3
note 4
note 5
note 3
note 3
2.7
2.7
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