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參數資料
| 型號： | PCD6003 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital telephone answering machine chip |
| 中文描述： | 數字電話應答機芯片 |
| 文件頁數： | 48/96頁 |
| 文件大小： | 385K |
| 代理商： | PCD6003 |
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2001 Apr 17
48
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
10.12.6 S
YNCHRONISATION
When enabled the receiver samples MIN with a frequency
f = 8
×
baud rate. The sampled values are shifted into an
8-bit shift register. This register is regularly checked
whether it contains samples that fulfil the Manchester
coding rule i.e. whether there is a LOW-to-HIGH or a
HIGH-to-LOW transition in the middle of the bitcell. The
receiver searches for 3 consecutive sets of 8 samples that
fulfil the Manchester coding rule. If these sets have been
found the clock is locked (MRL = 1) and the receiver starts
looking for the Manchester preamble pattern. From this
point on the receiver uses a Phase Locked Loop (PLL) to
adjustthesynchronisationaftereachreceivedManchester
bit.
10.13 LE control
The LE signal is the alternative output of P4.0 and can be
turned on with ALTP bit 1. The LE signal can be used to
connect to the E input of 68xxx microcontroller compatible
peripherals such as an LCD controller. If these peripherals
have a slow access time the LE signal can be made HIGH
earlier by setting bit 0 of ALTP. Bit 0 of ALTP will be
cleared by hardware after the execution of a MOVX
instruction. The ALTP register is described in more detail
in Section 16.2.
Figure 19 shows the LE signal shapes for early read
and/or write when the P4.0 alternative port function for LE
is selected. In Fig.19, the DTAM WR signal is only shown
for timing reference.
Neither WR nor RD are physically connected to the
display. The display RS and R/W pin can be connected to
Port 2 or MA pins (logic 0 after reset) and controlled by
software. The early LE timing hardware makes it possible
to access LCD drivers (or other peripheral devices with the
same interface) which require a large access time
(>3
×
microcontroller_CLK).
The display LE pin (P4.0) rising edge is determined by
software, by setting bit 0 and 1 of the ALTP SFR. In order
to latch the Port 0 data at the correct moment, the falling
edge is determined by internal DTAM hardware. This
generates for the LCD write operation an LE falling edge
at 0.5 of a microcontroller clock before the falling edge of
WR, such that the LCD data hold time (t
h
) requirement is
always fulfilled.
Figure 20 shows the LE signal shape for normal read
and/or write when the P4.0 alternate port function for LE is
selected. Again, the DTAM WR signal is only shown for
timing reference. Both the rising and falling edges of the
display LE pin (P4.0) are determined by hardware if only
bit 1 of the ALTP SFR is set. This generates for the LCD
write operation an LE falling edge at 0.5 of a
microcontroller clock before the falling edge of WR, such
that the LCD data hold time (t
h
) requirement is always
fulfilled.
The normal LE timing is actually the inverted value of
either the RD or WR signal. This timing can be used for
peripheral devices that have an access time of less than
3
×
microcontroller_CLK.
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相關代理商/技術參數 |
參數描述 |
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| PCD6003U | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital telephone answering machine chip |
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