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參數(shù)資料
| 型號： | PCD6003 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital telephone answering machine chip |
| 中文描述： | 數(shù)字電話應(yīng)答機(jī)芯片 |
| 文件頁數(shù)： | 81/96頁 |
| 文件大小： | 385K |
| 代理商： | PCD6003 |
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2001 Apr 17
81
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
Notes
1.
For the definition of the amplitude units (dB, dBm, dBm0, dBmp, dBm0p) see Section 13.1. All measurements are
performed with chopping switched on (PMTR2 = 04H) and unless mentioned otherwise, all measurements are
performed in RTC mode = 0 (CKCON.6 = 0) and at nominal supply voltage (V
DDA
= 2.50 V).
Maximum sinewave RMS level applied differentially between pins MICP and MICM. The analog-to-digital path gain
for CODEC2 is set to 7 dB (DTCON.1 = 1, DTCON.2 = 0). For larger input levels the output signal will saturate. For
higher analog-to-digital gain settings (including the microphone preamplifier), the maximum RMS input level will
decrease by the same amount as the gain will increase.
All input resistances represent the theoretical minimum which can be guaranteed by design. Note that given input
resistance values can vary depending on several conditions as processing, temperature and input signal shape. For
the measurement, the input signal is a 1 kHz sine wave which is AC coupled with a 1
μ
F capacitor (see Application
example in Fig. 36). The input resistance will increase when others than the noted gains are selected. For detailed
information on input resistances for all gain settings, refer to the PCD6003 application note which is available.
The differential resistance is seen between pins MICP and MICM. The minimum resistance will be seen for an
analog-to-digital path gain of 7 dB and will slightly increase for all other gain settings.
The common mode resistance is seen between MICP/MICM and V
SSA
. MICP and MICM are shorted. It corresponds
to RMICVDD ||RMICVSS (see Fig.36). The minimum resistance will be seen for an analog-to-digital path gain of
23/35 dB and will increase for all other gain settings.
Maximum sinewave RMS level applied differentially between pins LIFPIN and LIFMIN1/LIFMIN2. V
REF
is tuned to
2.0 V and the analog-to-digital path gain for CODEC1 is set to 7 dB (CDVC1.3 = 0, DTCON.5 = 0). For larger input
levels the output signal will saturate. For higher analog-to-digital gain settings, the maximum RMS input level will
decrease by the same amount as the gain will increase.
The differential resistance is seen between pins LIFPIN and LIFMIN1. The minimum resistance will be seen for an
analog-to-digital path gain of 23/35 dB and will increase for other gain settings.
The common mode resistance is seen between LIFPIN/LIFMIN1 and V
SSA
. LIFPIN and LIFMIN1 are shorted.
It corresponds to R
LIF1VDD
|| R
LIF1VSS
(see Fig.36). The minimum resistance will be seen for an analog-to-digital path
gain of 7 dB and will increase for other gain settings.
The differential resistance is seen between pins LIFPIN and LIFMIN2. The minimum resistance will be seen for an
analog-to-digital path gain of 23/35 dB and will increase for other gain settings.
10. The common mode resistance is seen between LIFPIN/LIFMIN2 and V
SSA
. LIFPIN and LIFMIN2 are shorted.
It corresponds to R
LIF2VDD
|| R
LIF2VSS
(see Fig. 36). The minimum resistance will be seen for an analog-to-digital path
gain of 7 dB and will increase for other gain settings.
11. Absolute typical gain for CODEC1 and CODEC2 for gain step 7dB (CDVC1.3 = 0, DTCON.5 = 0 and DTCON.1 = 1),
measured at the DR1/DR2 bitstream interface as defined in Fig.29 using a 1020 Hz sinewave. V
REF
is tuned to
2.00 V.
12. AbsolutetypicalgainforCODEC1andCODEC2forgainstep23 dB(CDVC1.3 = 1,CDVC2.3 = 0andDTCON.5 = 0,
DTCON.1 = 0), measured at the DR1/DR2 bitstream interface as defined in Fig.29 using a 1020 Hz sinewave. V
REF
is tuned to 2.00 V.
2.
3.
4.
5.
6.
7.
8.
9.
G(D/A)
delta digital-to-analog path gain from
DT1/DT2 to SPKR or LIFOUT
digital-to-analog idle channel noise
digital-to-analogsignal-to-(noise + total
harmonic distortion) ratio
notes 1 and 27
1
0
1
dB
F
(D/A)(idle)
S/(N+THD)
(D/A)(0)
S/(N+THD)
(D/A)(
40)
t
d(g)(D/A)
notes 1 and 28
notes 1 and 29
notes 1 and 30
42
89
80
50
500
80
dBmp
dBp
dBp
μ
s
digital-to-analog path group delay
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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