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參數(shù)資料
| 型號(hào)： | PCE84C487 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Microcontrollers for digital auto-sync and VST TV controller applications |
| 中文描述： | 微控制器的數(shù)字自動(dòng)同步和VST電視控制器的應(yīng)用 |
| 文件頁(yè)數(shù)： | 10/36頁(yè) |
| 文件大小： | 168K |
| 代理商： | PCE84C487 |
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1996 Feb 21
10
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
7
ANALOG (DC) CONTROL
The PCE84C486 has nine Pulse Width Modulated outputs
(PWM0 to PWM8) and the PCE84C487 has thirteen Pulse
Width Modulated outputs (PWM0 to PWM8 and
PWM10 to PWM13). These outputs are used for analog
control purposes e.g. brightness, contrast, H-shift, V-shift,
H-width, V-size, pin-cushion, trapezium, R (or G or B) gain
control, sound volume etc. Each PWM output generates a
pulse pattern with a programmable duty cycle.
The PWM outputs are specified below:
PWM0 to PWM3: 4 PWM outputs with 7-bit resolution
PWM4 to PWM7: 4 PWM outputs with 6-bit resolution
PWM8: 1 PWM output with 14-bit resolution
PWM10 to PWM13: 4 PWM outputs with 8-bit
resolution.
The 6 and 7-bit PWM outputs are described in Section 7.1;
the 8-bit PWM outputs are described in Section 7.2 and
the 14-bit PWM output is described in Section 7.3. A
typical PWM output application is described in Section 7.4.
7.1
6 and 7-bit PWM outputs
The block diagram for the 6 and 7-bit PWM outputs is
shown in Fig.6.
Pulse Width Modulated outputs PWM0 to PWM7 share
the same pins as Derivative Port lines DP00 to DP07,
respectively. Selection of the pin function as either a PWM
output or a Derivative Port line is achieved using the
appropriate PWMnE bit in the PWME1 Register (see
Table 8).
The polarity of the 6 and 7-bit PWM outputs is
programmable and is selected by the P7LVL or the P6LVL
bit in the CON2 Register (see Table 8). The state of the
P7LVL bit determines the polarity of the 7-bit PWMs; the
state of the P6LVL bit determines the polarity of the 6-bit
PWMs.
The duty cycle of each PWM output is dependent upon the
programmable contents of its associated data latch
(PWM0 to PWM7 Registers respectively). As the clock
frequency of each PWM circuit is
1
3
×
f
xtal
, the pulse width
of the pulse generated can be calculated as shown below.
Where (PWMn) is the decimal value held in the data latch.
Pulse width
3
PWMn
f
xtal
(
)
×
=
The maximum repetition frequency (f
PWM
) of the 6 and
7-bit PWM outputs is shown below.
For the 6-bit PWM outputs:
For the 7-bit PWM outputs:
7.2
8-bit PWM outputs
The block diagram for the 8-bit PWM outputs is shown in
Fig.8.
The 8-bit PWM outputs PWM10 to PWM13 (only available
with the PCE84C487) share the same pins as Derivative
Port lines DP24 to DP27, respectively. Selection of the pin
function as either a PWM output or a Derivative Port line is
achieved using the appropriate PWMnE bit in the
PWME2 Register (see Table 8). In the PCE84C486 the
contents of the PWME2 register should be set so that
these PWM outputs are disabled (i.e 00H).
The polarity of the 8-bit PWM outputs is programmable
and is selected by the P8LVL bit in the CON2 Register.
The duty cycle of each 8-bit PWM output is dependent
upon the programmable contents of its associated data
latch (PWM10 to PWM13 Registers respectively). As the
clock frequency of each PWM circuit is f
xtal
, the pulse
width of the pulse generated can be calculated as shown
below.
Where (PWMn) is the decimal value held in the data latch.
The maximum repetition frequency (f
PWM
) of the 8-bit
PWM outputs is shown below.
An 8-bit PWM output is driven HIGH when the value held
in its data latch is 00H. This is different to the 6 and 7-bit
PWM outputs which are driven LOW when their data
latches contain 00H.
f
PWM
f
192
=
f
PWM
f
384
---------
=
Pulse width
xtal
--Pf
)
=
f
PWM
f
256
=
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