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參數資料
| 型號： | PCE84C487 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Microcontrollers for digital auto-sync and VST TV controller applications |
| 中文描述： | 微控制器的數字自動同步和VST電視控制器的應用 |
| 文件頁數： | 21/36頁 |
| 文件大?。?/td> | 168K |
| 代理商： | PCE84C487 |
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1996 Feb 21
21
Philips Semiconductors
Objective specification
Microcontrollers for digital auto-sync and
VST TV controller applications
PCE84C486; PCE84C487
9
I
2
C-BUS INTERFACE
The PCE84C48X has an on-chip I
2
C-bus interface that
can be used in master or slave mode. Full details of the
I
2
C-bus are given in the document “The I
2
C-bus and how
to use it” This document may be ordered using the code
9398 393 40011.
The I
2
C-bus interface lines SDA and SCL share the same
pins as port lines DP20 and P10 respectively. Selection of
the pin function as either an I
2
C-bus line or a port line is
achieved using the SDAE and SCLE bits in Derivative
Register 22. Only port Option 2 is available for both of
these pins.
10 8-BIT COUNTER (T3)
The main application for this counter is in the frequency
measurement of the Hsync signal.
The block diagram of the 8-bit counter is shown in Fig.22.
A Schmitt trigger is used at the input for noise rejection and
also to shape the input signal into a square wave. The T3
input is sampled at a frequency of
1
3
×
f
osc
by the sample
clock which synchronizes the internal T3 clock and the
read operation of Derivative Register 24. The rising edge
of the input increments the ripple counter by 1.
The contents of T3 may be read using the instruction
MOV A, D24H. As soon as the data is read, the counter is
reset to zero. A counter overflow or Power-on-reset also
resets the counter contents to zero.
If the rising and falling edges of the input pulse are less
than 30 ns then the minimum pulse width that the T3 input
will recognise is 3/f
osc
+ 100 ns. If the system clock is
10 MHz then the minimum pulse width is 400 ns. In some
display modes, the active pulse width of the Hsync signal
can be less than 400 ns; in this situation some external
application circuitry may be required.
handbook, halfpage
tH
tL
0.9 VDD
0.1 VDD
0.1 VDD
0.9 VDD
tr
tr
tf
MGC719
tf
Fig.18 T3 input waveform.
Fig.19 Block diagram of the 8-bit counter (T3).
handbook, full pagewidth
MGC717
T3
Power-on-reset
sample clock
READ D24H
EMU
8-BIT COUNTER
RESET
Q0 to Q7
CK
Data bus
SYNCHRONISATION
CIRCUIT
T3 COUNTER
CONTROL CIRCUIT
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