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| 型號： | PCM1804DBR |
| 英文描述： | FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz STEREO A/D CONVERTER |
| 中文描述： | 全差分模擬輸入24位，192千赫立體聲A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 24/31頁 |
| 文件大小： | 470K |
| 代理商： | PCM1804DBR |
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PCM1804
SLES022A
–
DECEMBER 2001
24
www.ti.com
PRINCIPLES OF OPERATION
interface timing for DSD (continued)
tw(BCKH)
tw(BCKL)
t(CKDO)
t(BCKP)
0.5 VDD
0.5 VDD
DSDBCK
DSDL
DSDR
PARAMETERS
MIN
TYP
MAX
UNIT
DSDBCK period, t(BCKP)
DSDBCK pulse width high, tw(BCKH)
DSDBCK pulse width low, tw(BCKL)
Delay time DSDBCK falling edge to DSDL, DSDR valid, t(CKDO)
Rising time of all signals, tr
Falling time of all signals, tf
354.308
ns
177.154
ns
177.154
ns
–
5
15
ns
10
ns
10
ns
NOTES: A. Rising and falling time is measured from 10% to 90% of IN/OUT signals swing.
B. Load capacitance of DSDBCK/DSDL/DSDR signal is 10 pF.
Figure 40. Audio Data Interface Timing for DSD (Mast Mode Only)
synchronization with digital audio system for PCM
In slave mode, the PCM1804 operates under LRCK synchronized with the system clock SCKI. The PCM1804
does not need specific phase relationship between LRCK and SCKI, but does require the synchronization of
LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than
±
6 BCK during one sample period due to LRCK
or SCKI jitter, internal operation of the ADC halts within 1/f
S
and digital output is forced into BPZ code until
resynchronization between LRCK and SCKI is completed.
In case of changes less than
±
5 BCK, resynchronization does not occur and above digital output control and
discontinuity does not occur.
Figure 41 illustrates ADC digital output for loss of synchronization and resynchronization. During undefined
data, it may generate some noise in the audio signal. Also, the transitions of normal to undefined data and
undefined or zero data to normal make a discontinuity of data on the digital output. This may generate noise
in the audio signal. In master mode, synchronization loss never occurs.
HPF (low-cut filter) bypass control for PCM
The built-in function for dc component rejection can be bypassed by BYPAS (pin 12) control. In bypass mode,
the dc component of the input analog signal and the internal dc offset are also converted and output in the digital
output data.
Table 6. HPF Bypass Control
BYPASS
Low
High
LPF (HIGH-PASS FILTER) MODE
Normal (dc cut) mode
Bypass (through) mode
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