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參數資料
| 型號： | PCM1850 |
| 英文描述： | 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 X 2-CHANNEL MUX AND PGA |
| 中文描述： | 24位，96千赫立體聲A / D轉換器6 × 2通道的MUX和PGA |
| 文件頁數： | 5/30頁 |
| 文件大小： | 370K |
| 代理商： | PCM1850 |
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PCM1850
PCM1851
SLES108
MARCH 2004
www.ti.com
5
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
Supply voltage: V
CC
Supply voltage: V
DD
Ground voltage differences: AGND, DGND
–0.3 V to 6.5 V
–0.3 V to 4 V
±
0.1 V
Digital input voltage: LRCK, BCK, DOUT, OVER
Digital input voltage: RST, SCKI, MS (ADR)
(2)
, MC (SCL)
(2)
, MD (SDA)
(2)
, TEST0, TEST1
–0.3 V to (V
DD
+ 0.3 V) < 4 V
–0.3 V to 6.5 V
Analog input voltage: V
IN
L1–6, V
IN
R1–6
Analog input voltage: MOUTL, MOUTR, V
REF
1, V
REF
2, V
REF
S
Input current (any pins except supplies)
–3 V to (V
CC
+ 3 V) < 9 V
–0.3 V to (V
CC
+ 0.3 V) < 6.5 V
±
10 mA
–40
°
C to 125
°
C
–55
°
C to 150
°
C
150
°
C
260
°
C, 5 s
260
°
C
Ambient temperature under bias
Storage temperature
Junction temperature
Lead temperature (soldering)
Package temperature (IR reflow, peak)
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
PCM1850 (PCM1851)
ELECTRICAL CHARACTERISTICS
All specifications at T
A
= 25
°
C, V
CC
= 5 V, V
DD
= 3.3 V, master mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data, unless otherwise noted
PARAMETER
TEST CONDITIONS
PCM1850PJT PCM1851PJT
UNIT
MIN
TYP
MAX
DIGITAL INPUT/OUTPUT
DATA FORMAT
Audio data interface format
Left-justified, I
2
S, right-justified
Audio data bit length
16, 24
bits
Audio data format
MSB-first, 2s complement
f
S
Sampling frequency
16
48
96
kHz
256 f
S
384 f
S
512 f
S
768 f
S
4.096
12.288
24.576
System clock frequency
6.144
18.432
36.864
MHz
8.192
24.576
49.152
12.288
36.864
—
INPUT LOGIC
V
IH
(1)
V
IL
(1)
V
IH
(2) (3)
V
IL
(2) (3)
I
IH
(2)
I
IL
(2)
I
IH
(1) (3)
I
IL
(1) (3)
(1)
Pins 1, 2: LRCK, BCK (In slave mode, Schmitt-trigger input, with 50-k
typical pulldown resistor)
(2)
Pins 7, 31, 32: SCKI, MC/SCL (PCM1850/1851), MD/SDA (PCM1850/1851) (Schmitt-trigger input, 5-V tolerant)
(3)
Pins 8–10, 30: TEST0, TEST1, RST, MS/ADR (PCM1850/1851) (Schmitt-trigger input, with 50-k
typical pulldown resistor, 5-V tolerant)
2
V
DD
0.8
Input logic level
0
VDC
2
5.5
0
0.8
±
10
±
10
100
±
10
V
IN
= V
DD
V
IN
= 0
V
IN
= V
DD
V
IN
= 0
Input logic current
65
μ
A
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