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參數(shù)資料
| 型號： | PHD12N10E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | PowerMOS transistor |
| 中文描述： | 14 A, 100 V, 0.16 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | PLASTIC, SOT-428, 3 PIN |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 79K |
| 代理商： | PHD12N10E |
Philips Semiconductors
Product Specification
PowerMOS transistor
PHD12N10E
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suitable for surface
mounting. The device is intended for
use in Switched Mode Power
Supplies (SMPS), motor control,
welding, DC/DC and AC/DC
converters, and in general purpose
switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
V
DS
I
D
P
tot
T
j
R
DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state resistance
100
14
75
175
0.16
V
A
W
C
PINNING - SOT428
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
V
DS
Drain-source voltage
V
DGR
Drain-gate voltage
±
V
GS
Gate-source voltage
I
D
Drain current (DC)
I
D
Drain current (DC)
I
DM
Drain current (pulse peak value)
P
tot
Total power dissipation
T
stg
Storage temperature
T
j
Junction Temperature
CONDITIONS
-
R
GS
= 20 k
-
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
T
mb
= 25 C
-
-
MIN.
-
-
-
-
-
-
-
- 55
-
MAX.
100
100
30
14
10
56
75
175
175
UNIT
V
V
V
A
A
A
W
C
C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
TYP.
-
MAX.
2
UNIT
K/W
R
th j-a
pcb mounted, minimum
footprint
50
-
K/W
1
2
3
tab
d
g
s
September 1997
1
Rev 1.000
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