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參數(shù)資料
| 型號(hào)： | PHD63NQ03LT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | TrenchMOS logic level FET |
| 中文描述： | 68.9 A, 30 V, 0.0177 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252 |
| 封裝： | PLASTIC, SC-63, DPAK-3 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 104K |
| 代理商： | PHD63NQ03LT |
Philips Semiconductors
PHP/PHB/PHD63NQ03LT
TrenchMOS logic level FET
Product data
Rev. 01 — 14 June 2002
5 of 14
9397 750 09822
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5.
Characteristics
Table 4:
T
j
= 25
°
C unless otherwise specified
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
Characteristics
Conditions
Min
Typ
Max
Unit
I
D
= 250
μ
A; V
GS
= 0 V
T
j
= 25
°
C
T
j
=
55
°
C
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
°
C
T
j
= 175
°
C
T
j
=
55
°
C
V
DS
= 30 V; V
GS
= 0 V
T
j
= 25
°
C
T
j
= 175
°
C
V
GS
=
±
20 V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
°
C
T
j
= 175
°
C
V
GS
= 10 V; I
D
= 25 A;
Figure 7
and
8
30
27
-
-
-
-
V
V
V
V
V
V
V
GS(th)
gate-source threshold voltage
1
0.6
-
1.9
-
-
2.5
-
2.9
I
DSS
drain-source leakage current
-
-
-
0.05
-
10
1
500
100
μ
A
μ
A
nA
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
-
-
-
15
24
11
17.7
28.3
13
m
m
m
Dynamic characteristics
Q
g(tot)
total gate charge
Q
gs
gate-source charge
Q
gd
gate-drain (Miller) charge
C
iss
input capacitance
C
oss
output capacitance
C
rss
reverse transfer capacitance
t
d(on)
turn-on delay time
t
r
rise time
t
d(off)
turn-off delay time
t
f
fall time
Source-drain diode
V
SD
source-drain (diode forward) voltage I
S
= 25 A; V
GS
= 0 V;
Figure 12
t
rr
reverse recovery time
Q
r
recovered charge
I
D
= 50 A; V
DD
= 15 V; V
GS
= 5 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
9.6
4
3.2
920
275
110
12
140
10.5
14
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
Figure 11
V
DD
= 15 V; I
D
= 25 A; V
GS
= 4.5 V; R
G
= 5.6
-
-
-
0.95
23
12
1.2
-
-
V
ns
nC
I
S
= 10 A; dI
S
/dt =
100 A/
μ
s; V
GS
= 0 V
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