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參數資料
| 型號： | PI74ALVCH1622601 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 18-Bit Universal Bus Transceiver With 3-State Outputs |
| 中文描述： | 18位通用總線收發器和三態輸出 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 231K |
| 代理商： | PI74ALVCH1622601 |
1
PS8115B 02/03/98
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCH1622601 uses D-type latches and D-type flip-
flops with 3-state outputs to allow data flow in transparent, latched,
and clocked modes.
Data flow in each direction is controlled by Output Enable (OEAB
and OEBA), Latched Enable (LEAB and LEBA), and Clock
(CLKAB and CLKBA) inputs. The clock can be controlled by the
Clock Enable (CLKENAB and CLKENBA) inputs. For A-to-B
data flow, the device operates in the transparent mode when LEAB
is HIGH. When LEAB is LOW, the A data is latched if CLKAB is
held at a high or low logic level. If LEAB is low, the A-bus is stored
in the latch/flip-flop on the low-to-high transition of CLKAB.
When OEAB is low, the outputs are active. When OEAB is HIGH,
the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, CLKBA, and CLKENBA.
To reduce overshoot and undershoot, the inputs/outputs include
26
series resistors.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH1622601 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
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Product Features
PI74ALVCH1622601is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25°C
Inputs/Outputs have equivalent 26
series resistors,
no external resistors are required.
Bus Hold retains last active bus state during 3-state
eliminates the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
PI74ALVCH1622601
18-Bit Universal Bus Transceiver
With 3-State Outputs
Logic Block Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| PI74ALVCH162260 | 12-Bit To 24-Bit Multiplexed D-Type Latch with 3-STATE Outputs |
| PI74ALVCH16373 | 16-Bit Transparent D-Type Latch with 3-STATE Outputs |
| PI74ALVCH16373A | 8-Bit D-Type Latch |
| PI74ALVCH16373V | 8-Bit D-Type Latch |
| PI74ALVCH16827 | 20-Bit Buffer/Driver with 3-STATE Outputs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PI74ALVCH1622601A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Bus Transceiver |
| PI74ALVCH1622601SA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Bus Transceiver |
| PI74ALVCH1622601SV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Bus Transceiver |
| PI74ALVCH1622601V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Bus Transceiver |
| PI74ALVCH162260A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Bus Exchanger |
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