參數資料
| 型號： | PI74ALVCH16823A |
| 廠商： | Pericom |
| 文件頁數： | 1/7頁 |
| 文件大小： | 0K |
| 描述： | IC 18-BIT INTERFACE-F/F 56-TSSOP |
| 產品變化通告： | Product Discontinuation 17/Feb/2006 |
| 標準包裝： | 35 |
| 系列： | 74ALVCH |
| 功能： | 主復位 |
| 類型： | D 型總線 |
| 輸出類型： | 三態非反相 |
| 元件數： | 2 |
| 每個元件的位元數： | 9 |
| 頻率 - 時鐘： | 150MHz |
| 觸發器類型： | 正邊沿 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 包裝： | 管件 |
1
PS8103A 05/30/06
Logic Block Diagram
Product Description
The 18-bit PI74ALVCH16823 bus-interface flip-flop is designed for
2.3V to 3.6V VCC operation. It features 3-state outputs designed
specifically for driving highly capacitive or relatively low-
impedance loads. This device is particularly suitable for
implementing wider buffer registers, I/O ports, bidirectional bus
drivers with parity, and working registers.
The PI74ALVCH16823 can be used as two 9-bit flip-flops or one
18-bit flip-flop. With the Clock Enable (CLKEN) input LOW, the
D-type flip-flops enter data on the low-to-high transitions of the
clock. Taking CLKEN HIGH disables the clock buffer, thus
latching the outputs. Taking the Clear (CLR) input LOW causes the
Q outputs to go LOW independently of the clock.
A buffered Output Enable (OE) input can be used to place the nine
outputs in either a normal logic state (high or low logic levels) or
high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
The Output Enable (OE) input does not affect the internal operation
of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Product Features
Designed for low voltage operation, VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
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PI74ALVCH16823
18-Bit Bus-Interface Flip-Flop
with 3-State Outputs
06-0148
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PI74ALVCH16823V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit D-Type Flip-Flop |
| PI74ALVCH16825 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic | 18-Bit Buffer/Line Driver |
| PI74ALVCH16825A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9-Bit Buffer/Driver |
| PI74ALVCH16825V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9-Bit Buffer/Driver |
| PI74ALVCH16827 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:20-Bit Buffer/Driver with 3-STATE Outputs |
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