參數資料
| 型號： | PI74ALVTC16373A |
| 廠商： | Pericom |
| 文件頁數： | 1/10頁 |
| 文件大小： | 0K |
| 描述： | IC 16-BIT TRANSP LATCH 48-TSSOP |
| 產品變化通告： | Product Discontinuation Notice 29/May/2007 |
| 標準包裝： | 39 |
| 系列： | 74ALVTC |
| 邏輯類型： | D 型透明鎖存器 |
| 電路： | 8:8 |
| 輸出類型： | 三態 |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 獨立電路： | 2 |
| 延遲時間 - 傳輸： | 1ns |
| 輸出電流高，低： | 6mA，6mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 48-TSSOP |
| 包裝： | 管件 |
1
PS8355D
07/22/08
Product Description
The PI74ALVTC16373 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as two 8-bit latches or one 16-bit
latch. When the Latch Enable (LE) input is HIGH, the Q outputs
follow the (D) inputs. When LE is taken LOW, the Q outputs are
latched at the levels set up at the D inputs.
A buffered Output Enable (OE) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or
a high-impedance state in which the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the
increased drive provide the capability to drive bus lines without an
interface or pullup components. OE does not affect internal
operations of the latch. Old data can be retained or new data can be
entered while the ouputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VDD through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The family offers both I/O Tolerant, which allows it to operate in
mixed 1.8/3.6V systems, and “Bus Hold,” which retains the data
input’s last state whenever the data input goes to high-impedance,
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
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Product Features
PI74ALVTC family is designed for low-voltage operation,
VDD=1.8Vto3.6V
Supports Live Insertion
3.6V I/O Tolerant Inputs and Outputs
Bus Hold
High Drive, –32/64mA @ 3.3V
Uses patented noise reduction circuitry
Power-off high-impedance inputs and outputs
Industrial operation at –40°C to +85°C
Packaging (Pb-free and Green available):
– 48-pin 240 mil wide plastic TSSOP (A)
PI74ALVTC16373
16-Bit Transparent D-Type Latch
with 3-State Outputs
Logic Block Diagram
1LE
1Q1
1D
C1
1D1
To Seven Other Channels
1OE
1
48
47
2
2LE
2Q1
1D
C1
2D1
To Seven Other Channels
25
36
13
24
2OE
08-0291
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PI74ALVTC16373AE | 功能描述:閉鎖 16B Edge Trigered D type RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| PI74ALVTC16373AEX | 功能描述:閉鎖 16B Edge Trigered D type RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| PI74ALVTC16373K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit D-Type Latch |
| PI74ALVTC16373KE | 功能描述:閉鎖 16B Edge Trigered D type RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| PI74ALVTC16373KEX | 功能描述:閉鎖 16B Edge Trigered D type RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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