參數資料
| 型號： | PI74SSTU32866NBE |
| 廠商： | Pericom |
| 文件頁數： | 1/18頁 |
| 文件大小： | 0K |
| 描述： | IC 25BIT CONFIG REG BUFF 96LFBGA |
| 產品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標準包裝： | 285 |
| 邏輯類型： | 帶奇偶位的可配置寄存緩沖器 |
| 位數： | 25 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 96-LFBGA |
| 供應商設備封裝： | 96-LFBGA（13.5x5.5） |
| 包裝： | 托盤 |
1
PS8739B
11/21/05
Product Features
PI74SSTU32866 is a low-voltage device with VDD = 1.8V
Supports Low Power Standby Operation
All Inputs are SSTL_18 Compatible, except RST, C0, C1,
which are LVCMOS.
Output drivers are optimized to drive DDR-II DIMM loads
Packaging (Pb-free & Green):
— 96-Ball LFBGA (NB)
PI74SSTU32866 supports DDR2-533/400
Logic Block Diagram 1:2 Mode (Positive Logic)
PI74SSTU32866
25-bit 1:1 or 14-bit 1:2 Configurable
Registered Buffer with Parity
Product Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with
parity is designed for 1.7 V to 1.9 V VDD operation. All clock
and data inputs are compatible with the JEDEC standard for
SSTL_18. The control and reset (RST) inputs are LVCMOS. All
data outputs are 1.8 V CMOS drivers that have been optimized to
drive the DDR-II DIMM load, and meet SSTL_18 specifications.
The error (QERR) output is 1.8 V open-drain driver.
The PI74SSTU32866 operates from a differential clock (CK and
CK). Data are registered at the crossing of CK going high, and
CK going low.
The PI74SSTU32866 accepts a parity bit from the memory
controller on the parity bit (PAR_IN) input, compares it with
the data received on the DIMM-independent D-inputs (D2–D3,
D5–D6, D8–D25 when
C0 = 0 and C1 = 0; D2–D3, D5–D6, D8–D14 when C0 = 0 and
C1=1; or D1–D6, D8–D13 when C0 = 1 and C1=1) and indicates
whether a parity error has occurred on the open-drain QERR pin
(active low). The convention is even parity, i.e., valid parity is
defined as an even number of ones across the DIMM-independent
data inputs combined with the parity input bit. To calculate parity,
all DIMM-independent data inputs must be tied to a known logic
state.
When used as a single device, the C0 and C1 inputs are tied low.
In this configuration, parity is checked on the PAR_IN input
which arrives one cycle after the input data to which it applies.
The partial-parity-out (PPO) and QERR signals are valid three
cycles after the corresponding data inputs.
When used in pairs, the C0 input of the first register is tied low
and the C0 input of the second register is tied high. The C1 input
of both registers are tied high. Parity, which arrives one cycle
after the data input to which it applies, is checked on the PAR_IN
input of the first device. The PPO and QERR signals are produced
on the second device three clock cycles after the corresponding
data inputs. The PPO output of the first register is cascaded to
the PAR_IN of the second register. The QERR output of the first
register is left floating and the valid error information is latched
on the QERR output of the second register.
If an error occurs and the QERR output is driven low, it stays
latched low for two clock cycles or until RST is driven low. The
DIMM-dependent signals (DCKE, DCS, DODT, and CSR) are
not included in the parity check computation.
The C0 input controls the pinout configuration for the 1:2 pinout
from A configuration (when low) to B configuration (when high).
The C1 input controls the pinout configuration from 25-bit 1:1
(when low) to 14-bit 1:2 (when high).
In the DDR-II RDIMM application, RST is specified to be
completely asynchronous with respect to CK and CK. Therefore,
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| PI74SSTU32866NBEX | 功能描述:寄存器 25B 1:1 or 14B 1:2 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| PI74SSTV16857AE | 功能描述:寄存器 14Bit Lead Free Register Buffer RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| PI74SSTV16857AEX | 功能描述:寄存器 14Bit Lead Free Register Buffer RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| PI74SSTV16859A | 制造商:Pericom Semiconductor Corporation 功能描述:Registered Buffer Single 13-CH CMOS 64-Pin TSSOP Tube |
| PI74SSTV16859AE | 制造商:Pericom Semiconductor Corporation 功能描述:Registered Buffer Single 13-CH CMOS 64-Pin TSSOP Tube 制造商:Pericom Semiconductor Corporation 功能描述:13 to 26 Bit 2.3 to 2.7 V 2.8 ns Surface Mount Registered Buffer - TSSOP-64 |
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