- 您現在的位置：買賣IC網 > PDF目錄376255 > PSD312-70JM (意法半導體) High Speed PWM Controller 20-PLCC 0 to 70 PDF資料下載
參數資料
| 型號： | PSD312-70JM |
| 廠商： | 意法半導體 |
| 英文描述： | High Speed PWM Controller 20-PLCC 0 to 70 |
| 中文描述： | 低成本現場可編程微控制器外圍設備 |
| 文件頁數： | 26/85頁 |
| 文件大小： | 691K |
| 代理商： | PSD312-70JM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
PSD3XX Famly
23
12.0
Control Signals
(cont.)
12.5 A19/CSI
This pin is configured using PSDsoft to be either a chip select for the entire PSD device or
an additional PAD input. If your MCU can generate a chip-select signal, and you wish to
save power, use the PSD chip select feature. Otherwise, use this pin as an address or logic
input.
J
When configured as CSI (active-low PSD chip select): a low on this pin keeps the PSD
in normal operation. However, when a high is detected on the pin, the PSD
enters Power-down Mode. See Tables 7A and 7B for information on signal states
during Power-down Mode. See section 16 for details about the reduction of power
consumption.
J
When configured as A19, the pin can be used as an additional input to the PADs.
It can be used for address or logic. It can also be ALE/AS dependent or a transparent
input, which is determined by your PSDsoft design file. In A19 mode, the PSD is always
enabled.
Port
Configuration Mode(s)
State
AD0–A0/AD15/A15
All
MCU I/O
Tracking AD0/A0-AD7/A7
Latched Address Out
MCU I/O
Chip Select Outputs, CS0–CS7, CMOS
Chip Select Outputs, CS0–CS7, Open Drain
Address or Logic Inputs, A16-A18
Chip Select Outputs, CS8–CS10, CMOS only
Input (Hi-Z)
Unchanged
Input (Hi-Z)
Logic 1
Unchanged
Logic 1
Hi-Z
Input (Hi-Z)
Logic 1
Port Pins PA0–PA7
Port Pins PB0–PB7
Port Pins PC0–PC2
Table 7A. Signal States During Power-Down Mode
Internal Signal State
During Power-Down
Component
Internal Signal
PAD A and PAD B
CS0–CS10
Logic 1 (inactive)
CSADIN, CSADOUT1,
CSADOUT2, CSIOPORT,
ES0-ES7, RS0
Logic 0 (inactive)
All registers in CSIOPORT
address space, including:
Direction
Data
Page
PMR (turbo bit, ZPSD only)
N/A
All unchanged
Table 7B. Internal States During Power-down
NOTE:
N/A = Not Applicable
相關PDF資料 |
PDF描述 |
|---|---|
| PSD312-90J | Low Cost Field Programmable Microcontroller Peripherals |
| PSD312-90JI | High Speed PWM Controller 16-SOIC 0 to 70 |
| PSD312-90JM | Low Cost Field Programmable Microcontroller Peripherals |
| PSD312-A-15J | High Speed PWM Controller 16-SOIC 0 to 70 |
| PSD312-A-15JI | High Speed PWM Controller 16-SOIC 0 to 70 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD312-70LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD312-70LM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD312-70Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD312-70QI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD312-70U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
發布緊急采購，3分鐘左右您將得到回復。