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參數(shù)資料
型號(hào)： PSD913390MT
廠商： 意法半導(dǎo)體
英文描述： Quad CMOS to PECL Translator; Package: 20 LEAD PDIP; No of Pins: 20; Container: Rail; Qty per Container: 18
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù)： 66/110頁(yè)
文件大?。?/td> 1737K
代理商： PSD913390MT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
66/110
PSD Chip Select Input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft Ex-
press as PSD Chip Select Input (CSI). When Low,
the signal selects and enables the internal Flash
memory, EEPROM, SRAM, and I/O blocks for
READ or WRITE operations involving the PSD. A
High on PSD Chip Select Input (CSI, PD2) dis-
ables the Flash memory, EEPROM, and SRAM,
and reduces the PSD power consumption. How-
ever, the PLD and I/O signals remain operational
when PSD Chip Select Input (CSI, PD2) is High.
There may be a timing penalty when using PSD
Chip Select Input (CSI, PD2) depending on the
speed grade of the PSD that you are using. See
the timing parameter t
SLQV
in
Table 61., page 94
or
Table 62., page 95
.
Input Clock
The PSD provides the option to turn off CLKIN
(PD1) to the PLD to save AC power consumption.
CLKIN (PD1) is an input to the PLD AND Array and
the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is
not being used as part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocells block by setting Bits 4 or 5
to a 1 in PMMR0.
Input Control Signals
The PSD provides the option to turn off the input
control signals (CNTL0, CNTL1, CNTL2, Address
Strobe (ALE/AS, PD0) and DBE) to the PLD to
save AC power consumption. These control sig-
nals are inputs to the PLD AND Array. During
Power-down mode, or, if any of them are not being
used as part of the PLD logic equation, these con-
trol signals should be disabled to save AC power.
They are disconnected from the PLD AND Array
by setting Bits 2, 3, 4, 5, and 6 to a 1 in PMMR2.
Table 32. APD Counter Operation
APD Enable Bit
ALE PD Polarity
ALE Level
APD Counter
0
X
X
Not Counting
1
X
Pulsing
Not Counting
1
1
1
Counting (Generates PDN after 15 Clocks)
1
0
0
Counting (Generates PDN after 15 Clocks)
相關(guān)PDF資料
PDF描述
PSD9133V15JT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD9133V15MT Quad TTL-ECL Translator; Package: 20 LEAD PLLC; No of Pins: 20; Container: Tape and Reel; Qty per Container: 500
PSD9133V20MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD9133V70MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD9133V90MIT BBG ECL TRNSLATR 9BIT; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD9133V12JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD9133V12JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD9133V12MIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD9133V12MT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD9133V15JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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