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參數資料
型號: PSD913390MT
廠商: 意法半導體
英文描述: Quad CMOS to PECL Translator; Package: 20 LEAD PDIP; No of Pins: 20; Container: Rail; Qty per Container: 18
中文描述: Flash在系統可編程ISP的外設的8位微控制器
文件頁數: 89/110頁
文件大小: 1737K
代理商: PSD913390MT
89/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 56. READ Timing (3V devices)
Note: 1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing for 8031.
3. Any input used to select an internal PSD function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
Symbol
Parameter
Conditions
-12
-15
-20
Turbo
Off
Unit
Min
Max
Min
Max
Min
Max
t
LVLX
ALE or AS Pulse Width
26
26
30
ns
t
AVLX
Address Setup Time
(Note
3
)
9
10
12
ns
t
LXAX
Address Hold Time
(Note
3
)
9
12
14
ns
t
AVQV
Address Valid to Data Valid
(Note
3
)
120
150
200
+ 20
ns
t
SLQV
CS Valid to Data Valid
120
150
200
ns
t
RLQV
RD to Data Valid 8-Bit Bus
(Note
5
)
35
35
40
ns
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251
(Note
2
)
45
50
55
ns
t
RHQX
RD Data Hold Time
(Note
1
)
0
0
0
ns
t
RLRH
RD Pulse Width
38
40
45
ns
t
RHQZ
RD to Data High-Z
(Note
1
)
38
40
45
ns
t
EHEL
E Pulse Width
40
45
52
ns
t
THEH
R/W Setup Time to Enable
15
18
20
ns
t
ELTL
R/W Hold Time After Enable
0
0
0
ns
t
AVPV
Address Input Valid to
Address Output Delay
(Note
4
)
33
35
40
ns
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