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參數(shù)資料
型號(hào)： PSD913570MIT
廠商： 意法半導(dǎo)體
英文描述： BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù)： 11/110頁(yè)
文件大小： 1737K
代理商： PSD913570MIT
11/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Reset
48
I
Resets I/O Ports, PLD macrocells and some of the Configuration Registers. Must be Low
at Power-up.
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
28
27
25
24
23
22
21
I/O
These pins make up Port A. These port pins are configurable and can have the following
functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellAB0-7) outputs.
Inputs to the PLDs.
Latched address outputs (see Table
6
).
Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA in
burst mode.
As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.
D0/A16-D3/A19 in M37702M2 mode.
Peripheral I/O mode.
Note:
PA0-PA3 can only output CMOS signals with an option for high slew rate. However,
PA4-PA7 can be configured as CMOS or Open Drain Outputs.
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
I/O
These pins make up Port B. These port pins are configurable and can have the following
functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.
Inputs to the PLDs.
Latched address outputs (see Table
6
).
Note:
PB0-PB3 can only output CMOS signals with an option for high slew rate.
However, PB4-PB7 can be configured as CMOS or Open Drain Outputs.
PC0
20
I/O
PC0 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC0) output.
Input to the PLDs.
TMS Input
2
for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
PC1
19
I/O
PC1 pin of Port C. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellBC1) output.
Input to the PLDs.
TCK Input
2
for the JTAG Serial Interface.
This pin can be configured as a CMOS or Open Drain output.
Pin Name
Pin
Type
Description
相關(guān)PDF資料
PDF描述
PSD913570MT 1:9 TTL Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500
PSD913590JIT BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500
PSD913590JT PECL/TTL-TTL 1:8 Distribution Chip; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37
PSD913590MIT BBG ECL CLOCK DIST CHIP; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37
PSD913590MT PECL/TTL-TTL 1:8 Distribution Chip; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD913570MT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913590JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913590JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913590MIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913590MT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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