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參數資料
型號: Q67037-A1163
廠商: INFINEON TECHNOLOGIES AG
英文描述: MB 26C 26#20 PIN PLUG
中文描述: 2波段電視調諧器混頻器振蕩器鎖相環不平衡中頻放大器
文件頁數: 31/41頁
文件大小: 687K
代理商: Q67037-A1163
Reference
5 - 31
KTS6027-2, KTS6029-2
Wireless Components
Specification, July 2001
5.2
Programming
Table 5-4 Bit Allocation Read / Write
Byte
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
Ack
Write Data
Address Byte
1
1
0
0
0
MA1
MA0
0
A
Progr. Divider
Byte 1
0
N14
N13
N12
N11
N10
N9
N8
A
Progr. Divider
Byte 2
N7
N6
N5
N4
N3
N2
N1
N0
A
Control Byte
1
CP
T1
T0
CM
RSA
RSB
OS
A
Bandswitch
Byte
1).
x
x
x
x
P3
P2
P1
P0
A
Read Data
Address Byte
1
1
0
0
0
MA1
MA0
1
A
Status Byte
POR
FL
x
x
x
A2
A1
A0
A
1).
see Table 5-10 Bandswitching on page 33
Table 5-5 Description of symbols
Symbol
Description
MA0, MA1
Address selection bits (
see Table 5-6 Address selection on page 32
)
N14 to N0
programmable divider bits:
N = 2
14
x N14 + 2
13
x N13 + ..... + 2
3
x N3 + 2
2
x N2 + 2
1
x N1 + N0
CP
charge pump current:
bit = 0: charge pump current = 50 μA
bit = 1: charge pump current = 250μA
T1, T0
test bits (
see Table 5-7 Test modes on page 32
)
CM
charge pump mode bit (
see Table 5-9 Charge pump current on page 33
)
RSA, RSB
reference divider bits (
see Table 5-8 Reference divider ratio on page 32
)
OS
tuning amplifier control bit:
bit = 0: enable V
T
bit = 1: disable V
T
PLOW, PMID, PHIGH,
PFM,
see 5-10 on page 33
NPN ports control bits:
bit = 0: NPN open-collector output is inactive
bit = 1: NPN open-collector output is active
A0, A1, A2
ADC bits (
see Table 5-11 A/D converter levels on page 34
)
FL
PLL lock flag
bit = 1: loop is locked
POR
Power-on reset flag
flag is set at power-on and reset at the end of READ operation
x
don
t care
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